Nano/CMOS architectures using a field-programmable nanowire interconnect

Abstract

A field-programmable nanowire interconnect (FPNI) enables a family of hybridnano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid)approach proposed by Strukov and Likharev, allowing for simpler fabrication,more conservative process parameters, and greater flexibility in the choice ofnanoscale devices. The FPNI improves on a field-programmable gate array (FPGA)architecture by lifting the configuration bit and associated components out of thesemiconductor plane and replacing them in the interconnect with nonvolatile switches,which decreases both the area and power consumption of the circuit. This is anexample of a more comprehensive strategy for improving the efficiency of existingsemiconductor technology: placing a level of intelligence and configurability in theinterconnect can have a profound effect on integrated circuit performance, and can beused to significantly extend Moore’s law without having to shrink the transistors.Compilation of standard benchmark circuits onto FPNI chip models shows reduced area(8 × to 25 ×), reduced power, slightly lower clock speeds, and high defect tolerance—an FPNIchip with 20% defective junctions and 20% broken nanowires has an effectiveyield of 75% with no significant slowdown along the critical path, compared toa defect-free chip. Simulations show that the density and power improvementscontinue as both CMOS and nano fabrication parameters scale down, althoughthe maximum clock rate decreases due to the high resistance of very small(<10 nm) metallic nanowires.