Abstract
A novel direct digital frequency synthesizer (DDFS) based on a parabolic polynomial with an offset is proposed in this paper. A 16-segment parabolic polynomial interpolation is adopted to replace the traditional ROM-based phase-to-amplitude conversion methods. Besides, the proposed parabolic polynomial interpolation is realized in a multiplier-less structure such that the speed can be significantly improved. This work is manufactured by a standard 0.13 μm CMOS cell-based technology. The maximum clock rate is 161 MHz, the core area is 0.33 mm2, and the spurious free dynamic range (SDRF) is 117 dBc by physical measurements on silicon.
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