A high-speed subpixel edge detector implementation inside a FPGA

Abstract

In this paper we present a field programmable gate array (FPGA) implementation of a real-time subpixel edge detector. In comparison to existing edge detectors, the proposed method is implemented in hardware and its computational cost and complexity are very low. This in turn reduces the overall system cost quite significantly. The edge detection method is based on the approximation of the edge profile with a first-order linear function and then extrapolating the line to intercept a constant function. The position where both lines intersect will be the edge position. The detector is capable of processing a high-resolution CCD linear sensor at 2000 frames/s at the maximum clock rate of the sensor of 2 MHz. For that reason it is as fast as an analogue approach. The experimental results show that the proposed method can increase the resolution of an existing intelligent line camera by a factor of 6 or more. From the above it can be concluded that the proposed edge detector is effective for real-time, low-cost subpixel edge detection.