Semiconductor Device Fabrication Research Articles

Beyond Extreme Ultra Violet (BEUV) Radiation from Spherically symmetrical High-Z plasmas

Photo-lithography is a key technology for volume manufacture of high performance and compact semiconductor devices. Smaller and more complex structures can be fabricated by using shorter wavelength light in the photolithography. One of the most critical issues in development of the next generation photo-lithography is to increase energy conversion efficiency (CE) from laser to shorter wavelength light. Experimental database of beyond extreme ultraviolet (BEUV) radiation was obtained by using spherically symmetrical high-Z plasmas generated with spherically allocated laser beams. Absolute energy and spectra of BEUV light emitted from Tb, Gd, and Mo plasmas were measured with a absolutely calibrated BEUV calorimeter and a transmission grating spectrometer. 1.0 x 1012 W/cm2 is the optimal laser intensity to produced efficient BEUV light source plasmas with Tb and Gd targets. Maximum CE is achieved at 0.8% that is two times higher than the published CEs obtained with planar targets.

Mapping electron-beam-injected trapped charge with scattering scanning near-field optical microscopy.

Scattering scanning near-field optical microscopy (s-SNOM) has been demonstrated as a valuable tool for mapping the optical and optoelectronic properties of materials with nanoscale resolution. Here we report experimental evidence that trapped electric charges injected by an electron beam at the surface of dielectric samples affect the sample-dipole interaction, which has direct impact on the s-SNOM image content. Nanoscale mapping of the surface trapped charge holds significant potential for the precise tailoring of the electrostatic properties of dielectric and semiconductive samples, such as hydroxyapatite, which has particular importance with respect to biomedical applications. The methodology developed here is highly relevant to semiconductor device fabrication as well.

X-ray topographic study of defects in Si-based multilayer epitaxial power devices

Silicon based multilayered epitaxial structures are currently the main material for large-scale commercial fabrication of generally used power semiconductor devices such as fast recovery epitaxial diodes (FRED), isolate gate bipolar transistor (IGBT), power MOSFETs etc.Defects in silicon based multilayer epitaxial structures used as the initial material for power epitaxial-diffusion devices have been studied by X-ray topography techniques. We show that the dislocation nets with nonuniform distribution of dislocations both over thickness and layer square in the form of dense rows (dislocation walls) or slip bands were principal defects in the initial epitaxial layers and have influenced the electrical characteristics of power devices.The X-ray methods used in the work allow revealing and identifying growth and process defects in device structures, studying their distributions, analyzing their mutual interactions and obtaining valuable information on the nature and evolution of the defects during device structure fabrication processes. This information allowed us to optimize the choice of initial materials and processes aiming to reduce the content of critical electrically active structural defects in the crystals that can influence the parameters of fabricated semiconductor devices; we also increased process yield and tangibly improved semiconductor device operation reliability in severe conditions and emergency modes.

AxBAxB… pulsed atomic layer deposition: Numerical growth model and experiments

Atomic layer deposition (ALD) is widely used for the fabrication of advanced semiconductor devices and related nanoscale structures. During ALD, large precursor doses (>1000 L per pulse) are often required to achieve surface saturation, of which only a small fraction is utilized in film growth while the rest is pumped from the system. Since the metal precursor constitutes a significant cost of ALD, strategies to enhance precursor utilization are essential for the scaling of ALD processes. In the precursor reaction step, precursor physisorption is restricted by steric hindrance (mA1) from ligands on the precursor molecules. On reaction, some of these ligands are removed as by-products resulting in chemisorbed species with reduced steric hindrance (mA1 → mA2, where mA2 < mA1) and some of the initially hindered surface reaction sites becoming accessible for further precursor physisorption. To utilize these additional reaction sites, we propose a generalized AxBAxB… pulsed deposition where the total precursor dose (ΦA) is introduced as multiple x (x > 1, x ∈ I) short-pulses rather than a single pulse. A numerical first-order surface reaction kinetics growth model is presented and applied to study the effect of AxBAxB… pulsed ALD on the growth per cycle (GPC). The model calculations predict higher GPC for AxBAxB… pulsing than with ABAB… deposition. In agreement with the model predictions, with AxBAxB… pulsed deposition, the GPC was found to increase by ∼46% for ZrN plasma enhanced ALD (PEALD), ∼49% for HfO2 PEALD, and ∼8% for thermal Al2O3 ALD with respect to conventional ABAB… pulsed growth.

Characterization of half-pitch 15-nm metal wire circuit fabricated by directed self-assembly of polystyrene-block-poly(methyl methacrylate)

We developed a novel but simple sub-15-nm line-and-space (L/S) patterning process that requires neither special pinning guide materials to control the surface free energy nor a resist strip process after the guideline pattern fabrication. To perform process verification for practical semiconductor device manufacturing, we demonstrated electrical yield verification of the process and analyzed the causes of the process defects. One of the causes of open defects is narrower spaces in the upper layer. Improvements in the narrow space points originated from the critical dimension (CD) uniformity, and the roughness at the upper layer is effective for reduction of open defects. The radiofrequency (RF) power in pulsed mode and the depo-etch sequence in the reactive ion etching (RIE) process are effective in improving the surface roughness at the upper layer.

나노 반도체 소자를 위한 펄스 플라즈마 식각 기술

As the size of the semiconductor devices shrinks to nanometer scale, the importance of plasma etching process to the fabrication of nanometer scale semiconductor devices is increasing further and further. But for the nanoscale devices, conventional plasma etching technique is extremely difficult to meet the requirement of the device fabrication, therefore, other etching techniques such as use of multi frequency plasma, source/bias/gas pulsing, etc. are investigated to meet the etching target. Until today, various pulsing techniques including pulsed plasma source and/or pulse-biased plasma etching have been tested on various materials. In this review, the experimental/theoretical studies of pulsed plasmas during the nanoscale plasma etching on etch profile, etch selectivity, uniformity, etc. have been summarized. Especially, the researches of pulsed plasma on the etching of silicon, <TEX>$SiO_2$</TEX>, and magnetic materials in the semiconductor industry for further device scaling have been discussed. Those results demonstrated the importance of pulse plasma on the pattern control for achieving the best performance. Although some of the pulsing mechanism is not well established, it is believed that this review will give a certain understanding on the pulsed plasma techniques.

Analysis of the effect of symmetric/asymmetric CUSP magnetic fields on melt/crystal interface during Czochralski silicon growth

With the use of 300mm silicon wafers for industrial semiconductor device manufacturing, the Czochralski (Cz) crystal growth process has to be optimized to achieve higher quality and productivity. Numerical studies based on 2D global thermal models combined with 3D simulation of melt convection are widely used today to save time and money in the process development. Melt convection in large scale Cz Si growth is controlled by a CUSP or transversal magnetic field (MF) to suppress the melt turbulence. MF can be optimized to meet necessary characteristics of the growing crystal, in terms of point defects, as MF affects the melt/crystal interface geometry and allows adjustment of the pulling rate.Among the different knobs associated with the CUSP magnetic field, the nature of its configuration, going from symmetric to asymmetric, is also reported to be an important tool for the control of crystallization front. Using a 3D unsteady model of the CGSim software, we have studied these effects and compared with several experimental results. In addition, physical mechanisms behind these observations are explored through a detailed modeling analysis of the effect of an asymmetric CUSP MF on convection features governing the heat transport in the silicon melt.

Controllable Growth Orientation of SnS2 Flakes for Low‐Noise, High‐Photoswitching Ratio, and Ultrafast Phototransistors

The planar semiconductor device fabrication techniques promote us to control the growth orientation of layered metal dichalcogenide materials. Herein, an efficient approach to control the growth orientation of tin disulfide flake (F‐SnS2) and the applications in phototransistors is demonstrated. The in‐plane and vertical growth of F‐SnS2 can be mediated by adopting different substrates. In‐plane, F‐SnS2 is successfully grown on 2D substrates (mica, graphene, etc.) due to the van der Waals epitaxial growth. The vertical F‐SnS2 grown on 3D substrates is attributed to the impeding effect of dangling bonds. The secondary growth control experiments are carried out and the growth results further verify our explanations. The in‐plane F‐SnS2 is further applied in back‐gated phototransistors. The field‐effect mobility and current on/off ratio of back‐gated field‐effect transistors (BG‐FETs) reach 4 cm2 V‐1 s‐1 and 105. The as‐grown F‐SnS2 phototransistors show small photoswitching ratio (≈1.3), large dark current (≈μA), and slow response time (≈second order). The sluggish response is ascribed to long‐lived traps which may be induced by sulfur vacancy defects (V S). The as‐grown samples are further annealed in saturated sulfur atmosphere. The treatment can greatly suppress the deteriorating effect of long‐lived traps. The corresponding photoswitching ratio, dark current, and photoresponse time are improved to ≈40, pA order and millisecond order, respectively. The controllable orientation growth and efficient treatment technique are expected to be widely applied in other 2D metal dichalcogenide materials for high‐performance optoelectronic devices.

Structural change induced in LaAlO3 by ion implantation

Ion implantation is used for various purposes in manufacturing semiconductor devices such as MOS‐FETs. In the present study, the effects of implantation of P+ or B+ ions on the structural change of single‐crystal LaAlO3 were examined. The optical absorption edge located at ∼5.6 eV, which seems to correspond to the bandgap energy of LaAlO3, is hardly affected by the ion implantation. The X‐ray diffraction peak intensity at 2θχ=23.5° is decreased by the ion implantation. The intensities of three sharp photoluminescence (PL) peaks detected at 1.62, 1.65, and 1.69 eV, which appear only when the samples are crystalline, become smaller by ion implantation. However, the intensity of a broad PL peak at ∼2.8 eV due to the oxygen vacancy, which is detectable in both amorphous and crystalline samples, hardly changes after the ion implantation. These results indicate that the ion implantation degrades the crystallinity of LaAlO3. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley &amp; Sons, Inc.

Electrical yield verification of half-pitch 15 nm patterns using directed self-assembly of polystyrene-block-poly(methyl methacrylate)

A novel half-pitch (HP) 15 nm line pattern multiplication process with simple process steps and low cost-of-ownership using a polystyrene-block-poly(methyl methacrylate) lamellar block copolymer was developed to carry out process verification of directed self-assembly lithography on a 300 mm wafer for practical semiconductor device manufacturing. Electrical yield verification of HP 15 nm metal wire circuits fabricated by the HP 15 nm line pattern multiplication process was carried out on a 300 mm wafer. The electrical yield verification revealed the viability of the HP 15 nm line pattern multiplication process from the perspective of the total practical performance including critical dimension control, defect control, local placement error, line width roughness, line edge roughness, and process windows in the pattern transfer process.

Structure of the velocity distribution of sheath-accelerated secondary electrons in an asymmetric RF-dc discharge

Low-pressure capacitively-coupled discharges with additional dc bias applied to a separate electrode are utilized in plasma-assisted etching for semiconductor device manufacturing. Measurements of the electron velocity distribution function (EVDF) of the flux impinging on the wafer, as well as in the plasma bulk, show a thermal population and additional peaks within a broad range of energies. That range extends from the thermal level up to the value for the ‘ballistic’ peak, corresponding to the bias potential. The non-thermal electron flux has been correlated to alleviating the electron shading effect and providing etch-resistance properties to masking photoresist layers. ‘Middle-energy peak electrons’ at energies of several hundred eV may provide an additional sustaining mechanism for the discharge. These features in the electron velocity (or energy) distribution functions are possibly caused by secondary electrons emitted from the electrodes and interacting with two high-voltage sheaths: a stationary sheath at the dc electrode and an oscillating self-biased sheath at the powered electrode. Since at those energies the mean free path for large-angle scattering (momentum relaxation length) is comparable to, or exceeds the size of the discharge gap, these ‘ballistic’ electrons will not be fully scattered by the background gas as they traverse the inter-electrode space. We have performed test-particle simulations in which the features in the EVDF of electrons impacting the RF electrode are fully resolved at all energies. An analytical model has been developed to predict existence of peaked and step-like structures in the EVDF. Those features can be explained by analyzing the kinematics of electron trajectories in the discharge gap. Step-like structures in the EVDF near the powered electrode appear due to accumulation of electrons emitted from the dc electrode within a portion of the RF cycle, and their subsequent release. Trapping occurs when the RF sheath voltage exceeds the applied bias, and is decreasing. The secondary electrons originating from the dc-biased surface also form a peak near the energy equal to the bias potential. Additional peaks, at lower energies, are formed by the electrons emitted from the RF electrode and eventually escaping to it. The latter can be grouped according to the number of bounces between the sheaths during their residence time in the discharge. Each of such groups may give rise to an individual peak in the distribution. The trap-and-release theory developed in this paper provides a convincing explanation for the observations of the ballistic and ‘middle energy peak’ electrons detected in experiments.

Clean Hands [MicroBusiness

Discusses the importance of cleanliness and spotless conditions that are required in the production and manufacturing of semiconductor devices and materials.

(Invited) Neutral Beam Technology – Defect-free Nanofabrication for Novel Nano-materials and Nano-devices

In the fabrication of semiconductor devices, reactive plasmas arewidely used in key processes suchasmicrofabrication, surface modificationand film deposition, and there are now demands for processingprecision at the atomic layer level, and for deposition accuracy thatallows the control of structures at the molecular level. However, inultra-miniature nanoscale devices that will become the mainstream inthe future, the use of plasma processes can cause serious problemssuch as abnormal etching and breakdown of insulation films by theaccumulation of ions or electrons emitted from the plasma , also the formation of surface defects (dangling bond) of overa few tens nm in depth by exposure to ultraviolet (UV) emissions fromthe plasma. In particular, since nano-scale devices have a larger surfacearea compared with the bulk material, plasma processes can havea large influence on the electrical and optical properties of devices dueto process-induced defects caused by ultraviolet exposure,since future nano-devices will require size control of three-dimensionalstructures at the atomic layer level, it will be absolutely essential tocontrol surface chemical reactions with high precision and selectivity at the atomic layer level. To achieve charge-free and UV photon irradiation damage-free processes, we have developed a new neutral beam generation system based on my discovery that neutral beams can be efficiently generated from the acceleration of negative ions produced in pulsed plasmas. Using the neutral beam processing, we successfully demonstrated sub-50nm damage-free gate electrode etching, damage-free Si channel etching for 45 nm fin-FETs, ultra-thin gate dielectric film formation for 32 nm fin-FETs, damage-free low dielectric film deposition for 22 nm FETs, and low-damage surface modification of carbon materials (including nanotubes, graphenes and organic moleculers) for future nanodevices. More recently we have investigated processing technologies based on the combination of biotechnology with neutral-beam-based nano-processes, i.e., bio-nano processes, for future nanoelectronics devices and successfully achieved the fabrication of sub-10-nm-diameter and high density Si, Ge, GaAs, InGaAs and Graphene nanodisk (nanodot) array structures. The quantum effects of these nano-scaled structures were shown to manifest themselves at room temperature due to the damage-free surfaces made possible by the neutral beam processes. Now, by using these nanodisk structures, we are actively developing “Novel Quantum Effect Devices”, such as quantum dot solar cell for high energy conversion efficiency of more than 45 % and quantum dot laser. This paper introduces the neutron beam generation technique developed by S. Samukawa [1], and discusses its application to nanoprocessing and nanodevices that have recently been vigorously pursued. We conclude our developed neutral beam process is indispensable to progress atomic layer pure surface reactions for atomic layer process such as etching (ALE) and deposition (ALD).We are actively developing ultra-low-damage nanofabrication techniques using neutral beam technology that tap into the essential nature of nano-materials and nano-structures, and developing innovative nanodevices. S. Samukawa, ECS Journal of Solid State Science and Technology, 4 (6) N5089 (2015).

Etching of Silicon Nitride in 3D NAND Structures

3D NAND structures present a unique difficulty in semiconductor device manufacturing. One method of production consists of cylindrical structures made of alternating layers of silicon dioxide (SiO2) and silicon nitride (SiN) with a core of SiO2. As part of the device manufacturing process the SiN is etched away, leaving the SiO2 core with disc-shaped SiO2 fins. Due to material selectivity requirements of etching only the SiN while leaving the SiO2 unchanged, the process of choice is often immersion in a high-concentration hot phosphoric acid (H3PO4) bath with a silica additive to inhibit SiO2 etching, which with proper tuning can have selectivity of greater than 100:1 for etching SiN:SiO2. Like all wet etch processes, uniformity of the process is a constant concern. One of our goals in this paper is to show how we use experimental measurements and simulations to better understand what parameters have the most effect on the process, and how we can use that knowledge to improve the process. Experimentally we have measured the etch rate of blanket SiN and SiO2 wafers. We fit the etch rate data to Arrhenius models to quantify the etch rate of SiN and SiO2 films. Simulations of the etch process on both blanket wafers and patterned wafers showed that the etch rate is the same and doesn’t depend on feature geometry. In this paper we propose a simple chemical reaction and diffusion mechanism that explains the experimental observations of the etched structures. The uniformity of the SiN etching between the top and the bottom of the 3D NAND stacks indicates that the reaction rate is much slower than the rate of diffusion of reactants and products into and out of the structure, so the etching is a reaction-controlled mechanism. This indicates within-wafer uniformity and wafer-to-wafer uniformity variations as being primarily due to differences of temperature within the bath. We also conducted simulations of the etching of the SiN in the 3D NAND structure and the liquid flow in the bath to model and explain this mechanism. In these simulations we varied the rate of the surface reaction of H3PO4 etching SiN, and showed that for a fast reaction rate that the structure would etch from the top to the bottom as the overall reaction rate become diffusion limited, while for a slow reaction rate the entire structure would etch uniformly, showing it to be a reaction limited process. Another issue with SiN etching in an H3PO4 bath is that the etch rate of SiO2 depends highly on the concentration of silica, in fact the bath is generally pre-seeded with silica in order to achieve a lower SiO2 etch rate, though if above a critical concentration deposition is known to occur. Based on a study of silica chemistry, it may be possible for silica deposition to occur even when below the critical concentration. This would be a film that would grow on a SiO2 surface but would later dissolve back into solution. We propose a mechanism that explains the formation and later disappearance of the growth film on the SiO2 surface as a result of the etching of the SiN and the formation of silica byproducts into a sol/gel network. Sol/gels have the unique property of their ability to form in an area of locally high flux, and then later dissolve over a much longer time scale. The difference in forward and backward reaction rates of the sol/gel film formation and disillusion, respectively, are such that the system is never in equilibrium. Thus, even though all the silica can dissolve in the phosphoric acid at equilibrium, the silica formed from the SiN etching forms into a sol/gel polymer network that only slowly dissolves after SiN etching has stopped. We discuss the implications of this sol/gel oxide film for further process improvement. With better theoretical understanding of the SiN etching and possible silica sol/gel formation and dissolution process, we now have tools to better optimize the phosphoric acid bath, improving both etching uniformity and necessary process time. Figure 1

Superconformal Film Growth: Insights Provided By Seiras

State of the art manufacturing of semiconductor devices involves electrodeposition of copper for device wiring and more recently for through-silicon-vias (TSVs). The process depends on the use of electrolyte additives that affect the local deposition rate thereby resulting in superconformal, or bottom–up “superfilling” of trenches and vias. In the case of Damascene processing of submicron features the deposition process is explained by the recently developed curvature enhanced accelerator coverage (CEAC) mechanism. The model stipulates that 1.) the growth velocity is proportional to the local accelerator, or catalyst, surface coverage and 2.) the catalyst remains segregated at the metal/electrolyte interface during copper deposition. For growth on non-planar geometries this leads to enrichment of the catalyst on advancing concave surfaces and dilution on advancing convex sections; thereby giving rise to bottom-up superfilling of recessed surface features such as trenches and vias. In the case of larger features other avenues for feature filling become available that will be outlined in some detail. Despite the success of these superconformal growth processes much remains to be known concerning the detailed molecular nature of the competitive co-adsorption processes involved in both the suppression and acceleration of the metal deposition reaction. The application of in situ surface science tools such as in situ STM and SEIRAS towards a better understanding of the additive interactions will also be detailed. The interaction between adsorbed anions, polyether suppressors, sulfonate terminated thiol/disulfide accelerator additves and water at the growing interface reveal the critical role of hydrophobic/hydrophilic interactions in controlling the growth velocity during metal deposition. The talk will conclude with an overview of the current understanding of additive adsorption, consumption and/or deactivation dynamics relevant to superfilling and microstructural evolution in both Damascene and TSV Cu processing.

Experimental observations on the crystalline structures of YAlO3 single crystal at high temperatures

To understand the effects of thermal annealing on a high-permittivity gate insulating material YAlO3, its single crystal was annealed at various high temperatures ranging from 900 to 1300 °C and was examined by various instrumental analyses such as X-ray diffraction, infrared absorption spectroscopy, laser confocal microscopy, and atomic force microscopy. As a result, it was clarified that the crystalline YAlO3 takes at least three structures in a temperature range up to 1300 °C. Namely, it is perovskite below 1160 °C, at which the garnet structure starts to appear, while an unknown structure appears at 1250 °C. On the other hand, the sample surface also shows drastic changes if the temperature exceeds 1160 °C. Furthermore, many elliptical spots are induced after the annealing at 1200 or 1250 °C. Moreover, hydroxyl groups are generated at 1300 °C. It is desirable to take these structural changes into account in determining the annealing temperature of YAlO3 for various industrial purposes such as the manufacture of semiconductor devices.

Aerosol-assisted extraction of silicon nanoparticles from wafer slicing waste for lithium ion batteries.

A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

Application of Directed Self‐Assembly Lithography to Semiconductor Device Manufacturing Process

SUMMARYDirected self‐assembly (DSA) lithography has recently entered the spotlight as one of the most promising new generation lithography candidates, with the potential for fabrication of semiconductor device patterns down to sub‐30 nm. In this report, the latest experimental and simulation results on the contact hole shrinking process using DSA are demonstrated.

Overview of atomic layer etching in the semiconductor industry

Atomic layer etching (ALE) is a technique for removing thin layers of material using sequential reaction steps that are self-limiting. ALE has been studied in the laboratory for more than 25 years. Today, it is being driven by the semiconductor industry as an alternative to continuous etching and is viewed as an essential counterpart to atomic layer deposition. As we enter the era of atomic-scale dimensions, there is need to unify the ALE field through increased effectiveness of collaboration between academia and industry, and to help enable the transition from lab to fab. With this in mind, this article provides defining criteria for ALE, along with clarification of some of the terminology and assumptions of this field. To increase understanding of the process, the mechanistic understanding is described for the silicon ALE case study, including the advantages of plasma-assisted processing. A historical overview spanning more than 25 years is provided for silicon, as well as ALE studies on oxides, III–V compounds, and other materials. Together, these processes encompass a variety of implementations, all following the same ALE principles. While the focus is on directional etching, isotropic ALE is also included. As part of this review, the authors also address the role of power pulsing as a predecessor to ALE and examine the outlook of ALE in the manufacturing of advanced semiconductor devices.

Feasibility study of sub-10-nm-half-pitch fabrication by chemically amplified resist processes of extreme ultraviolet lithography: II. Stochastic effects

Line edge roughness (LER) rapidly increases in the sub-10-nm-half-pitch region of resist processes used for the fabrication of semiconductor devices. Sub-10-nm fabrication with high throughput is a challenging task. In this study, the stochastic effects (LER and stochastic defect generation) of chemically amplified resist processes in the sub-10-nm-half-pitch node were investigated, assuming the use of extreme ultraviolet (EUV) lithography. The latent images were calculated by a Monte Carlo method on the basis of the sensitization and reaction mechanisms of chemically amplified EUV resists. 7-nm-half-pitch fabrication by chemically amplified resist processes is considered to be feasible. However, significant improvement in the efficiencies of the conversion processes from optical images to resist images is required.