Semiconductor Device Fabrication Research Articles

Exploration of the evolution of nanotechnology from a patent co-classification perspective

AbstractIn an era of dramatic changes, enterprises tend to rely on tracking the main trends of technological evolution to maintain a competitive advantage when confronted with the impact of competing new and old technologies and disruptive innovation. This paper explores the evolution of nanotechnology via an analysis of the patent co-classification from the database at the United States Patent and Trademark Office (USPTO). A total of 518 patents on nanotechnology were analyzed. The trend of nanotechnology and the patents of high betweenness centrality were identified. It was found that the technical classifications of “semiconductor device manufacturing” and “chemistry of inorganic compounds” have the highest potential for future growth. These classifications have shown a stable number of filed patents and have become the mainstream in nanotechnology development since the 1980s. Furthermore, this study also showed that the patents owned by the US comprise a significant portion of the applications in the major technical classifications, which has played an important role in the evolution of nanotechnology. The results demonstrated that an analysis of the patent network can be a useful tool for both understanding and predicting the trend of an emerging technology.

A High Sensitivity and Compact Real Time Gas Concentration Sensor for Semiconductor and Electronic Device Manufacturing Process

Various metal-organic(MO) gases are used in manufacturing processes of electronic device such as semiconductors, power devices, LEDs and displays. These MO gas are generally supplied with bubbling, and the in-line concentration sensor is used to control their concentration [1]. However, due to diversification of semiconductor processes, adaptation to various MO gas, high sensitivity and high speed sampling are required [2]. Various MO gases have the light absorption in the ultraviolet light wavelength region of 400 nm or less, and we developed a concentration sensor by measuring ultraviolet absorbance. Fig. 1 shows the developed concentration sensor unit. A small gas cell with a good sealing performance against reactive gases was prepared, and a detection circuit section was fabricated by adopting a charge amplifier method to obtain high sensitivity, instead of the commonly-used transimpedance amplifier method. So far, we demonstrated that highly sensitivity to commonly used MO gases such as Bis(cyclopentadienyl)magnesium[Cp2Mg] with the response speed of 400 msec or less could be realized using the developed sensor [3]. In this abstract, we report on the possibility of measuring the concentration of Zr and Hf MO gases that are commonly used in semiconductor High-k process. The measurement was carried out by heating the gas cell with an optical path length of 50 mm at 50 ° C. In the measurement, the LED with a wavelength λ of 360 nm and the LED with λ of 255 nm were switched and irradiated alternatively. The output voltage difference of the two wavelength LEDs according to concentration was taken into the PC with 16bit output and data processing was performed. The sampling period was 400 msec. For Zr MO gas, Tetrakis(ethylmethylamino)zirconium[TEMAZ] and Tris(dimethylamino)cyclopentadienylzirconium[ZAC] were evaluated and for the Hf MO gas, and Tetrakis (ethylmethylamino)hafnium[TEMAH] was evaluated for the Hf MO gas. Fig.2 shows the evaluation results for TEMAZ. Fig. 2 (a) shows the output of the concentration sensor unit when 41.5ppm-TEMAZ and 100%-Ar are switched at intervals of about 5 min by the valve operation. Good repeatability for the output signals were obtained for each gases in each periods. Fig. 2 (b) shows a calibration curve for TEMAZ, where the output signal as a function of the TEMAZ concentration is shown. The calibration curve was superior in linearity. Also, because the charge amplifier method was adopted, we confirmed that very small minimum detection sensitivity of 95 ppb could be achieved by taking into account of 5 σ of circuit noise. Similarly, we found that the minimum detection sensitivities of ZAC and TEMAH were 141 ppb and 80 ppb, respectively. The results demonstrated that the developed concentration sensor is very useful for realizing the precise measurement of various MO gases in semiconductor manufacturing. [1] T. W. Woods et al., ECS Transactions, 3 (7) 215-217, 2006. [2] V. Miikkulainen et al., J. Appl. Phys. 113, 021301 (2013) [3] H. Ishii et al., IEEE Sensors 2016 (IEEE), 877-879, 2016. Figure 1

Superconformal Cu Electrodeposition: Seiras and STM Study of the Polyether-SPS-Cl System

State of the art manufacturing of semiconductor devices involves electrodeposition of copper for device wiring and chip stacking. The success of the electroplating process depends on electrolyte additives that affect the local deposition rate to yield void-free superconformal, or bottom–up filling of trenches and vias that comprise 3D interconnects. Quantitative chemical process models have been shown to be effective in describing the filling of high aspect ratio features that range from nanometers to millimeters in scale. Nevertheless, much remains to be known about the molecular nature of the additives and the competitive, co-adsorption dynamics involved in both suppression and acceleration of metal deposition. Accordingly, a variety of surface science tools, such as STM and SEIRAS, are being used to investigate additive function. These studies point to controlling interface hydrophilicity as a key principle in the design and operation of additives used for superconformal film growth.

Experimental Study for Mosfet with Ellipsoidal Layout

Many efforts in research are conducted and high investments are currently made to create increasingly smaller MOSFETs and with better analog and digital electrical characteristics. There are several ways to try to achieve these goals, among them are the use of new materials for the manufacture of semiconductor devices, new planar and threedimensional structures of MOSFETs and new manufacturing processes. Another innovative and fully-Brazilian alternative is the use of new and different layouts for the implementation of these devices. Among the different layouts proposed, we have the ellipsoidal that is the evolution of other layouts, such as the hexagonal and the octagonal. Recently, experimental studies on the advantages and disadvantages between the ellipsoidal layout MOSFET and its corresponding rectangular were conducted showing promising results for this new layout. The main idea of diamond and ellipsoidal layouts was to take advantage of the cornering effects to potentiate the drain current of the device. This effect is called the LCE (Longitudinal Corner Effect) and it is responsible for increasing the longitudinal electric field along the channel of the MOSFET, thus increasing the velocity of drift from the movable carriers in the channel, which ultimately results in a higher drain current (IDS), transconductance, on-state resistance, etc. In addition to the effect cited above, others are still incorporated into the structure of MOSFET ellipsoidal, which can enhance their electric performance. Examples of these new effects are the PAMDLE (Parallel connection of MOSFETs with Different channel Length Effect) and the LECRE (Leakage Current Reduction Effect), which further enhances the drain current around the margins of the device and reduces the leakage current when the device operates in the cut-off region, respectively. The main objective of this study then is to investigate the benefits of this geometry in relation to conventional geometry, to apply this innovative layout in analog and digital integrated circuits. For conducting the study, devices of the same technology were characterized in the ellipsoidal and conventional geometries, in the same bias conditions and through the normalization of curves by the aspect ratio (W/L). For the characterization of the devices was used a chip with the manufacturing technology of TSMC (Taiwan Semiconductor), with a minimum size of 180 nm. These devices were manufactured via MOSIS, through the MEP program. Through the system of electrical characterization of the Keithley were obtained the curves ID x VD and ID x VG for the same conditions of polarizations on both devices. After the normalization of the curves by the aspect ratio, several parameters of the devices were compared to establish how much the gate geometry influenced the electric behavior of the ellipsoidal MOSFET. Figure 1 shows the values of the drain current in function of the gate tension for both devices, with a drain tension of 50 mV. Table I presents the values obtained for the currents of the on-state and off-state (ION and IOFF), as well as the figure of merit ION/IOFF. A comparative study between Ellipsoidal MOSFET and conventional counterpart was performed. The ellipsoidal layout style proved to be a better alternative for the improvement of the performance of devices. Figure 1

HCl Flow-Induced Phase Change of α-, β-, and ε-Ga2O3 Films Grown by MOCVD

Precise control of the heteroepitaxy on a low-cost foreign substrate is often the key to drive the success of fabricating semiconductor devices in scale when a large low-cost native substrate is not available. Here, we successfully synthesized three different phases of Ga2O3 (α, β, and e) films on c-plane sapphire by only tuning the flow rate of HCl along with other precursors in an MOCVD reactor. A 3-fold increase in the growth rate of pure β-Ga2O3 was achieved by introducing only 5 sccm of HCl flow. With continuously increased HCl flow, a mixture of β- and e-Ga2O3 was observed, until the Ga2O3 film transformed completely to a pure e-Ga2O3 with a smooth surface and the highest growth rate (∼1 μm/h) at a flow rate of 30 sccm. At 60 sccm, we found that the film tended to have a mixture of α- and e-Ga2O3 with a dominant α-Ga2O3, while the growth rate dropped significantly (∼0.4 μm/h). The film became rough as a result of the mixture phases since the growth rate of e-Ga2O3 is much higher than that of α-Ga2O3...

IMPROVED PROCESS FLOW FOR FORMATION OF BIPOLAR STATIC INDUCTION TRANSISTOR

The improved process flow differs from the known ones in the fact that the same photomask is used for formation of a channel stopper and metal contacts. Such approach has made it possible not only to decrease a number of the used phototomasks but it has also permitted to obtain a device with the required electrical characteristics. The paper presnts results of device and process simulation of bipolar static induction transistor (BSIT) manufactured in accordance with the improved process flow, measuring data of electrophysical parameters of its experimental samples and also comparison of simulation results with experimental data. At present there is a large quantity of software products that permit to perform physico-topological simulation of semiconductor structures. The device-process simulation is considered as a part of such simulation and it allows prior to obtaining experimental samples to determine process flow parameters at which the investigated structure will have necessary electrical parameters and characteristics. Thus the device-process simulation represents a certain “virtual production” for manufacturing semiconductor devices and microcircuits beginning from the startup stage of semiconductor wafer at production site and finishing by electrical characteristics measurements of the obtained structure. The BSIT device simulation being an analog of direct measurements of current-voltage characteristics has been performed with help of program system MOD-1D developed by the author. The BSIT model based on the fundamental system of semiconductor equations is mainly used for calculation of the BSIT current-voltage characteristics direct branch and its parameters and charge carrier recombination is described by Shockley – Read – Hall expression and equation depicting the Auger recombination process.

OFET Preparation by Lithography and Thin Film Depositions Process

The length of the channel OFET based thin film is determined during preparation takes place using the technique of lithography and mask during the metal deposition process. The lithography technique is the basic process steps in the manufacture of semiconductor devices. Lithography is the process of moving geometric shapes mask pattern to a thin film of material that is sensitive to light. The pattern of geometric shapes on a mask has specifications, as follows: long-distance source and drain channels varied, i.e. 100 μm, the width of the source and drain are made permanent. Bottom contact OFET structure has been created using a combination of lithography and thin film deposition processes.

Most Advanced Semiconductor Surface Cleaning : Current Problems and Future Prospects

With semiconductor-device geometry shrinking and becoming more complex, conventional aqueous cleaning/drying of semiconductor surfaces tends to collapse high-aspect-ratio nano-structures due to the surface tension of rinsing water. This is one of the most significant problems in leading-edge semiconductor manufacturing. Some current problems in the most advanced semiconductor surface cleaning and several possible solutions to overcome the shortcomings of water-based cleaning will be described and discussed with special emphasis on non-aqueous or dry wafer-surface cleaning technologies to prevent the pattern collapse problem. While semiconductor device geometry will scale down to 5-nm and below in the near future, completely different materials and device structures will be introduced in the semiconductor-device manufacturing. Larger diameter (450-mm) silicon wafers will also be employed in the future. There will be more research challenges and opportunities in developing innovative semiconductor surface cleaning and conditioning technologies for these future applications.

Defect-induced Stress Imaging in Single and Multi-crystalline Semiconductor Materials

Residual stress is a key feature which has to be taken into account in all steps of fabrication and processing of semiconductor materials and devices. The photo-elastic microscope SIREX (Scanning Infrared Stress Explorer) measures the depolarization of the light of an infrared laser probe caused by stress-induced birefringence in the sample. Subsequently, a map visualizes the in-plane optical anisotropy induced by stress. Hence, the system is applied as non-destructive tool to map stress distributions with high lateral resolution (3µm) and highest possible stress sensitivity (0.1 kPa). The so-called multi-polarization analysis results in maps of the in-plane maximum shear stress magnitude Δσ and the direction of the principal stress components. These maps can reveal the local stress fields of buried defects and their alignment in distinctive crystallographic directions. The fields are usually at least one order of magnitude larger in extension than the related defects themselves. Examples of extended defect structures in different crystalline semiconductor materials are presented in this paper. The emphasis has been put on line-shaped structures such as slip lines and twins which are partly accompanied by either tensile or compressive point-like stress sources. These structures are showing model characteristics for developing formal procedures of data and image processing under industrial conditions.

Brush Deformation Effects on Poly Vinyl Acetal Brush Scrubbing

PVA brush scrubbing techniques are widely used in cleaning processes for semiconductor device manufacturing. These cleaning processes are typically monitored by measuring the forces or torques generated during PVA brush scrubbing. In this paper, we discuss whether these measured parameters reflect the real contact conditions during scrubbing. We measured the shear forces generated by brush sliding. The shear forces were strongly correlated with brush deformation. In addition, brush rotation greatly suppressed brush deformation and shear force. This result indicates that a portion of the shear force was generated by brush deformation and not contact conditions. We also measured the torque generated by the PVA brush rotation on a surface. We concluded that these types of measurements, which reduced brush deformations, were suitable for evaluating contact conditions.

Measurements and modeling of the impact of radical recombination on silicon nitride growth in microwave plasma assisted atomic layer deposition

High material quality silicon nitride thin film deposition by plasma enhanced atomic layer deposition (PEALD) is necessary for many advanced semiconductor device and memory fabrication applications. Understanding film growth mechanism is quite important not only for the device production control but also device performance due to the strong correlation of film growth speed and film chemical property. Nevertheless, predicting film deposition rates, let alone film quality, is difficult as quantitative surface reaction mechanisms are still not well known and the species fluxes that play the central role in film growth are not easy to measure. In this paper, the authors describe how a plasma reactor model for the nitridation step required in PEALD of silicon nitride can be combined with a phenomenological site balance model to predict film growth rate variation with some key process parameters. The relative insensitivity of growth rates to plasma power are explained by competing destruction and regeneration mechanisms for NH3, an important nitrogen source in Si3N4 growth. The model also helps to reveal why H2 can be important.

Dynamics of Radical Ions of Hydroxyhexafluoroisopropyl-Substituted Benzenes.

Fluorination of resist materials is an effective method used to enhance the energy deposition of extreme ultraviolet (EUV) light in the fabrication of next-generation semiconductor devices. The dynamics of radical ions are important to understand when considering the radiation-chemistry of the resist materials using EUV and electron beam lithography. Here, the dynamics of the radical anions and cations of benzenes with one or two 2-hydroxyhexafluoroisopropyl groups (HFABs) were studied using radiolysis techniques. The formation of dimer radical cations was observed only in the monosubstituted benzene solutions of 1,2-dichloroethane. If the compound contained more than two substituents, it was found to hinder the necessary π-π overlapping. Pulse radiolysis of HFABs in tetrahydrofuran showed a characteristic spectral shift of the radical anion within the region of several hundred nanoseconds. From the results of low-temperature spectroscopy and density functional calculations, it is suggested that excess electrons of the 2-hydroxyhexafluoroisopropyl group of the radical anions cause dissociation into neutral radicals.

Patterning approach for detecting defect in device manufacturing

Compact handheld devices which were a dream in the past are now a reality; this has been enabled by miniaturization of circuit architectures including power devices. Scaling down of the design feature sizes does come with a price with an increase in systematic defects during chip manufacturing. There are generally two methods of inline defect detection adopted to monitor the semiconductor device fabrication—optical inspection and electron beam inspection. The optical inspection uses ultra-violet and deep ultra-violet (UV/DUV) light to find patterning defects on the wafer. While the electron-beam inspection uses electron charge and discharge measurement to find electrical connection defects, both are a costly procedure in terms of resources and time. The physical limit of feature resolution of the optical source is now making the defect inspection job difficult in miniaturized application specific integrated circuit (ASIC). This study is designed to test the patterning optimization approach on both inspection platforms. Using hotspot analysis weak locations are identified in the full chip design, and then they are verified in the inline wafer inspection. The criterion for hot-spot determination is also discussed in this paper.

Speciation of CuCl and CuCl2 Thiol-Amine Solutions and Characterization of Resulting Films: Implications for Semiconductor Device Fabrication.

Thiol-amine mixtures are an attractive medium for the solution processing of semiconducting thin films because of their remarkable ability to dissolve a variety of metals, metal chalcogenides, metal salts, and chalcogens. However, very little is known about their dissolution chemistry. Electrospray ionization high-resolution tandem mass spectrometry and X-ray absorption spectroscopy were employed to identify the species formed upon dissolution of CuCl and CuCl2 in 1-propanethiol and n-butylamine. Copper was found to be present exclusively in the 1+ oxidation state for both solutions. The copper complexes detected include copper chlorides, copper thiolates, and copper thiolate chlorides. No complexes of copper with amines were observed. Additionally, alkylammonium ions and alkylammonium chloride adducts were observed. These findings suggest that the dissolution is initiated by proton transfer from the thiol to the amine, followed by coordination of the thiolate anions with copper cations. Interestingly, the mass and X-ray absorption spectra of the solutions of CuCl and CuCl2 in thiol-amine were essentially identical. However, dialkyl disulfides were identified by Raman spectroscopy as an oxidation product only for the copper(II) solution, wherein copper(II) had been reduced to copper(I). Analysis of several thiol-amine pairs suggested that the dissolution mechanism is quite general. Finally, analysis of thin films prepared from these solutions revealed persistent chlorine impurities, in agreement with previous studies. These impurities are explained by the mass spectrometric finding that chloride ligands are not completely displaced by thiolates upon dissolution. These results suggest that precursors other than chlorides will likely be preferred for the generation of high-efficiency copper chalcogenide films, despite the reasonable efficiencies that have been obtained for films generated from chloride precursors in the past.

Atomic-scale finishing of carbon face of single crystal SiC by combination of thermal oxidation pretreatment and slurry polishing

Single-crystal silicon carbide (4H-SiC) has a range of useful physical, mechanical and electronic properties that make it a promising material for fabrication of next-generation semiconductor devices. In this work, we report a hybrid polishing process combining thermal oxidation pretreatment and soft abrasive polishing to realize the damage-free and atomic-scale smooth finishing of the carbon face of 4H-SiC. By thermal oxidation pretreatment, the hardness of the carbon face has been reduced from 4.6GPa to 1.7GPa, which enables highly efficient polishing using CeO2 slurry. For conventional CeO2 slurry polishing without pretreatment, scratches still existed after a long polishing duration for 16h. The probable scratch removal mechanism in CeO2 slurry polishing has been proposed based on surface morphology changes during polishing. Whereas a scratch-free surface with well-ordered SiC atomic steps was obtained within a short polishing duration of only 3h when polishing was conducted on a thermally oxidized surface. Our results demonstrate that hybrid polishing combining surface pretreatment and soft abrasive polishing is a promising approach to realize the damage-free and atomic-scale smooth finishing of the carbon face of 4H-SiC.

(Invited) Superconformal Film Growth:Impact of Additives and Deposition on Hydrophilicity

State of the art manufacturing of semiconductor devices involves electrodeposition of copper for device wiring and more recently for through-silicon-vias (TSVs). The process depends on the use of electrolyte additives that affect the local deposition rate thereby resulting in superconformal, or bottom–up “superfilling” of trenches and vias. Quantitative descriptions based on mass balance analysis of the additives and their effect on the local deposition rate have been shown to be effective for describing Damascene feature filling (CEAC, Curvature Enhanced Coverage Mechanism) and larger scale TSV filling (S_NDR, S-shaped negative differential resistance models). Despite the success of these processes much remains to be known concerning the detailed molecular nature of the competitive co-adsorption processes involved in both the suppression and acceleration of the metal deposition reaction. Accordingly, the application of in situ surface science tools such as in situ STM and SEIRAS towards a better understanding of the additive interaction will also be detailed. These studies show that the addition of Cl- to an acidified CuSO4 electrolyte displaces co-adsorbed SO4 2--water species from the Cu surface. The rapidly formed ordered halide overlayer disrupts the adjacent solvent hydrogen bond network to create a hydrophobic interface that facilitates co-adsorption of polyethers, such as poly(ethylene glycol) (PEG), polyoxamers (EPE), polyoxamines (TET), that are known to block the Cu deposition reaction by limiting access of Cu2+ aq to the underlying metal surface. When challenged by bis-(3-sodium sulfopropyl disulfide) (SPS), or mercaptopropane sulfonate (MPS), competitive disulfide/thiol adsorption leads to disruption and displacement of the polymer suppressor. The disulfide/thiol head group tethers SPS/MPS to the surface, via Cu adatoms or defects in the Cl- covered surface, while the SO3 - terminal group makes the interface hydrophilic which accounts for its anti-suppressor action. The potential dependence of competitive SPS adsorption and its dependence on the strength of polyether adsorption were measured.

Electroless UPD Monolayer Deposition - a Prelude to Highly Selective Electroless Atomic Layer Deposition Process

The improved understanding of nucleation kinetics has led to various discoveries in which the thin film growth was manipulated to enhance the evolution of atomically flat epitaxial overlayers. Exploiting some of these results has led to invention of several new methods and protocols for electrodeposition where underpotentially deposited (UPD) monolayer is used as a mediator, surfactant or sacrificial template. The one successful example is so called “deposition via surface limited redox replacement (SLRR) of UPD monolayer,” which gained a lot of applications for synthesis of noble metal thin films with different functionalities. This protocol/method represents the combination of the potential controlled step (formation of UPD monolayer) and the electroless step (SLRR of UPD monolayer by more noble metal ions, i.e., galvanic displacement). However, our studies show that there is still a lot of room left for improvements and further simplifications. These should expand application of this deposition protocol in many areas where traditional atomic layer deposition (ALD) process has been used. In this talk we present results demonstrating an electroless ALD process in which a Pb UPD monolayer is used as a reducing agent and sacrificial material in SLRR reaction with noble metal ions such as Pt, Pd, and Ru and Cu. The full deposition cycle involves sequential exposure of the substrate such as Cu and Ru to the solution for electroless Pb UPD monolayer deposition and then to the solution for SLRR reaction and noble metal deposition. This results in an overall deposition of controlled amount of noble metal which is the function of the areal density of deposited Pb monolayer and stoichiometry of the SLRR reaction. Therefore, the process mimics, to a great extent, the standard ALD cycle where adsorption of the metal precursors and surface catalyzed reaction are replaced by electroless Pb UPD monolayer deposition and SLRR reaction. If the two-step SLRR cycle is repeated an arbitrary number of times, a highly compact, smooth, and conformal noble metal thin film can be grown. The deposition process is highly selective to the metal substrates at which Pb forms an UPD monolayer providing an advantage when certain integration requirements are considered. The process is designed for (but not limited to) aqueous solutions with fairly simple and stable chemistry that can be easily scaled up to any size and shape of the substrate surface. Results demonstrating details and underlying phenomena controlling this process will be discussed. In addition, an example of a high quality of Pt, Pd, Cu and Ru films grown on Cu and Ru substrate will be shown, as well as the applications of this process for metallization of structures relevant to semiconductor device fabrication.

High‐Precision Temperature‐Controllable Metal‐Coated Polymeric Molds for Programmable, Hierarchical Patterning

Nanofabrication is an indispensable process in nanoscience and nanotechnology. Unconventional lithographic techniques are often used for fabrication as alternatives to photolithography because they are faster, more cost‐effective, and simpler to use. However, these techniques are limited in scalability and utility because of the collapse of preprinted structures during step‐and‐repeat processes. This study proposes a new class of temperature‐controllable polymeric molds that are coated with a metal such that any site‐specific patterning can be accomplished in a programmable manner using selective contact‐dewetting lithography. The lithography allows sub‐100 nm patterning, step‐and‐repeat processing, and hierarchical structure fabrication. The programmable feature of the lithography can be utilized for the structural coloring and shaping of objects. Large‐area programmable patterning, semiconductor device manufacturing, and the fabrication of iridescent security devices would benefit from the unique features of the proposed strategy.

Artificial Synapses with Short- and Long-Term Memory for Spiking Neural Networks Based on Renewable Materials.

Emulation of biological synapses that perform memory and learning functions is an essential step toward realization of bioinspired neuromorphic systems. Artificial synaptic devices have been developed based mostly on inorganic materials and conventional semiconductor device fabrication processes. Here, we propose flexible biomemristor devices based on lignin by a simple solution process. Lignin is one of the most abundant organic polymers on Earth and is biocompatible, biodegradable, as well as environmentally benign. This memristor emulates several essential synaptic behaviors, including analog memory switching, short-term plasticity, long-term plasticity, spike-rate-dependent plasticity, and short-term to long-term transition. A flexible lignin-based artificial synapse device can be operated without noticeable degradation under mechanical bending test. These results suggest lignin can be a promising key component for artificial synapses and flexible electronic devices.

A review of nanoimprint lithography for high-volume semiconductor device manufacturing

Abstract Imprint lithography has been shown to be a promising technique for the replication of nanoscale features. Jet and flash imprint lithography (J-FIL) [jet and flash imprint lithography and J-FIL are trademarks of Molecular Imprints, Inc.] involves the field-by-field deposition and exposure of a low-viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid, which then quickly flows into the relief patterns in the mask by capillary action. After this filling step, the resist is cross-linked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Included on the list are overlay, throughput, and defectivity. The most demanding devices now require an overlay of better than 4 nm, 3σ. Throughput for an imprint tool is generally targeted at 80 wafers/h. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. The purpose of this paper is to report the status of throughput and defectivity work and to describe the progress made in addressing overlay for advanced devices. To address high-order corrections, a high-order distortion correction (HODC) system is introduced. The combination of applying magnification actuation to the mask and temperature correction to the wafer is described in detail. Examples are presented for the correction of K7, K11, and K17 distortions as well as distortions on actual device wafers.