Semiconductor Device Fabrication Research Articles

Microwave plasma assisted process for cleaning and deposition in future semiconductor technology

The epitaxial growth of silicon layers is an important step in the fabrication of semiconductor devices. For conventional silicon epitaxy, high temperatures, up to 900 °C are necessary. However, in future, semiconductor technology epitaxy processes at lower temperatures are required to increase the integration density. The goal of this study was to investigate microwave plasma assisted processes for the selective removing of thin silicon oxide, the cleaning of silicon surfaces and the depositing of high quality silicon films. The main focus was to apply these processes for low temperature epitaxy. All processes, such as oxide removal, cleaning and deposition, were done in one chamber and with microwave plasma assistance. In order to remove silicon dioxide, the etching behavior of hydrogen, fluorine, and hydrogen/fluorine plasma was studied. It was shown, that with hydrogen/fluorine plasma, the best selectivity of oxide to silicon was reached. The deposition process of silicon was studied by growing μc-Si films. The process was characterized and optimized by spectral ellipsometry. After a successful characterization of all process steps, silicon epitaxy layers have been grown with in-situ removal of native oxide and in-situ surface cleaning. The temperature for all process steps was reduced below 450 °C.

Electronic Quality Improvement of Highly Defective Quasi‐Mono Silicon Material by Phosphorus Diffusion Gettering

Quasi‐mono silicon (QM‐Si) attracts interest as a substrate material for silicon device processing with the promise to yield single‐crystalline silicon quality with multicrystalline silicon cost. A significant barrier to widespread implementation of QM‐Si is ingot edge‐contamination caused by the seed material and crucible walls during crystal growth. This work aims to recover the scrap material in QM‐Si manufacturing with a process easily adaptable to semiconductor device manufacturing. A phosphorus diffusion process at 870 °C for 60 min significantly improves the electronic quality of a QM‐Si wafer cut from a contaminated edge brick. The harmonic minority carrier recombination lifetime of the wafer, a key predictor of ultimate device performance, experiences a tenfold increase from 17 to 178 µs, which makes the scrap QM‐Si material usable for device fabrication. Local areas with suboptimal (<50 µs) lifetimes remaining can be further improved by a high temperature anneal before the phosphorus diffusion process.

Determination of Trace Elements in Sintered and Single-Crystal Silicon Carbide by Laser Ablation in Liquid Inductively Coupled Plasma Mass Spectrometry

Laser ablation in liquid (LAL) sampling method transformed hard-to-digest materials to soluble particles, and thus allowed for smooth decomposition by acid digestion. LAL sampling is useful to generate nanoparticles from samples with less contamination. After acid digestion, trace elements in the LAL-sampled particles were analyzed by solution nebulization inductively coupled plasma mass spectrometry (ICPMS). For the first time we demonstrated that LAL-ICPMS can be used to determine trace elements in hard-to-digest samples; sintered SiC and single-crystal SiC. Results obtained by laser ablation ICPMS and LAL-ICPMS were compared in terms of accuracy and detection limits. The detection limits of LAL-ICPMS were 0.04 - 0.4 μg g-1 for Al, Ti, Cr, Mn, Fe, Co, Ni, Cu, Sr, Y, Zr, and W. LAL-ICPMS is expected to be used to control contamination in the manufacturing of semiconductor devices.

Simulation and experimental verification of silicon dioxide deposition by PECVD

Deposition of silicon dioxide in high-density plasma is an important process in integrated circuit manufacturing. A software named CFD-ACE was used to simulate the mechanism of plasma in the chamber of plasma enhanced chemical vapor deposition (PECVD) system, and the evolution of the feature profile was simulated based on CFD-TOPO. Simulation and experiment of silicon dioxide that deposited in SiH4/N2O mixture by PECVD system was researched. The particle density, energy and angular distribution in the chamber were simulated and discussed. We also studied how the depth/width ratio affected the step coverage of the trench and analyzed the deposition rate of silicon dioxide on the feature scale. X-ray photoelectron spectroscopy (XPS) was used to analyze the elemental composition of thin films. Images of the feature profiles were taken by scanning electron microscope (SEM). The simulation results were in good agreement with experimental, which could guide the semiconductor device manufacture.

Excited states and quantum confinement in room temperature few nanometre scale silicon single electron transistors

Single nanometre scale quantum dots (QDs) have significant potential for many ‘beyond CMOS’ nanoelectronics and quantum computation applications. The fabrication and measurement of few nanometre silicon point-contact QD single-electron transistors are reported, which both operate at room temperature (RT) and are fabricated using standard processes. By combining thin silicon-on-insulator wafers, specific device geometry, and controlled oxidation, <10 nm nanoscale point-contact channels are defined. In this limit of the point-contact approach, ultra-small, few nanometre scale QDs are formed, enabling RT measurement of the full QD characteristics, including excited states to be made. A remarkably large QD electron addition energy ∼0.8 eV, and a quantum confinement energy ∼0.3 eV, are observed, implying a QD only ∼1.6 nm in size. In measurements of 19 RT devices, the extracted QD radius lies within a narrow band, from 0.8 to 2.35 nm, emphasising the single-nanometre scale of the QDs. These results demonstrate that with careful control, ‘beyond CMOS’ RT QD transistors can be produced using current ‘conventional’ semiconductor device fabrication techniques.

Rinsing of High-Aspect-Ratio Features on Patterned Wafers

A comprehensive process model is developed to simulate the mechanism and the dynamics of rinsing and cleaning of deep and narrow structures on patterned substrates. This process is critical in a number of applications such as post-etch cleaning of patterned wafers during the manufacturing of semiconductor devices. The model takes into account various mass transport mechanisms including convection and diffusion/dispersion that occur simultaneously with various surface interactions such as adsorption and desorption of impurities on the substrate surfaces. The influences of charged species in the bulk and on the surface, and their induced electric field that affect both transport and surface interactions, are included in this paper. The results of this paper illustrate the model usefulness and potentials to predict the change in the rinse time and efficiency with changes in the key operational parameters such as temperature, concentration, flow rate, and mass transfer on the wafer surface. Ammonium hydroxide on SiO 2 surface is used as the model system in this study because of its wide application; however, the model can be used for analyzing the rinsing of other impurities by simply changing the model parameter inputs.

Решения для исследований и производства полупроводниковых приборов, МЭМС, дисплеев

Решения для исследований и производства полупроводниковых приборов, МЭМС, дисплеев

Novel EUV Photoresist for Sub-7 nm Node

Extreme ultraviolet (EUV) lithography has been recognized as a promising candidate for the manufacturing of semiconductor devices as LS/CH pattern for 7 nm node and beyond. EUV lithography is ready for high volume manufacturing stage. For the high-volume manufacturing of semiconductor devices, significant improvement of sensitivity and line edge roughness (LWR) and Local CD Uniformity (LCDU) is required for EUV resist. It is well-known that the key challenge for EUV resist is the simultaneous requirement of ultrahigh resolution (R), low line edge roughness (L) and faster sensitivity (S). Especially sensitivity and good roughness is important for EUV lithography high volume manufacturing. We are trying to improve sensitivity and LWR/LCDU from many directions. From material side, we found that both sensitivity and LWR/LCDU are simultaneously improved by controlling acid diffusion length and efficiency of acid generation using novel resin and PAG. And optimizing EUV integration is one of the good solution to improve sensitivity and LWR/LCDU. We are challenging to develop new multi-layer materials to improve sensitivity and LWR/LCDU. Our new multi-layer materials are designed for best performance in EUV lithography system. From process side, we found that sensitivity was substantially improved maintaining LWR applying novel type of chemical amplified resist (CAR) and process. EUV lithography evaluation results obtained for new CAR EUV interference lithography. And, metal containing resist is one possibility to break through sensitivity and LWR trade off. In this paper, we will report the recent progress of sensitivity and LWR/LCDU improvement of JSR novel EUV resist and process.

Patterning approach for detecting defect in device manufacturing

Compact handheld devices which were a dream in the past are now a reality; this has been enabled by miniaturization of circuit architectures including power devices. Scaling down of the design feature sizes does come with a price with an increase in systematic defects during chip manufacturing. There are generally two methods of inline defect detection adopted to monitor the semiconductor device fabrication --- optical inspection and electron beam inspection. The optical inspection uses ultra-violet and deep ultra-violet (UV/DUV) light to find patterning defects on the wafer. While the electron- beam inspection uses electron charge and discharge measurement to find electrical connection defects, both are a costly procedure in terms of resources and time. The physical limit of feature resolution of the optical source is now making the defect inspection job difficult in miniaturized application specific integrated circuit (ASIC). This study is designed to test the patterning optimization approach on both inspection platforms. Using hotspot analysis weak locations are identified in the full chip design, and then they are verified in the inline wafer inspection. The criterion for hot-spot determination is also discussed in this paper. DOI: 10.21883/FTP.2017.12.45192.8203

Far-field analysis of third-order distributed feedback terahertz quantum cascade lasers

The single lobe far-field patterns produced from terahertz quantum cascade lasers (QCLs) are greatly demanded for various applications, such as imaging, data transmission, etc. However, for a ridge waveguide terahertz QCL, the far-field beam divergence is large due to the fact that the waveguide aperture is far smaller than the terahertz wavelength. This is the case typically for double-metal waveguide terahertz QCL which emits terahertz photons in almost every direction in the space. Even for a single plasmon waveguide terahertz QCL, the divergence angle is as large as 30 in both horizontal and vertical direction. Here, in this work we design and fabricate a double metal third-order distributed feedback terahertz QCL emitting around 4.3 THz, and investigate the characteristics of the longitudinal and transverse modes. This work aims to achieve high beam quality for terahertz QCL by exploiting the third-order distributed feedback geometry, and in the meantime to achieve single longitudinal mode operation. The electromagnetic field distribution in the waveguide is modelled by employing a finite element method. The mode selection mechanism is studied by using the eigen frequency analysis, and the far-field beam is simulated by applying the near-field to far-field Fourier transform technique. The QCL active region used in this work is based on the resonant-phonon design, which is grown by a molecular beam epitaxy (MBE) system on a semi-insulating GaAs (100) substrate. The wafer bonding and traditional semiconductor device fabrication technology, i.e., optical lithography, electron beam evaporation, lift-off, wet and dry etching, are used to process the MBE-growth wafer into the third-order distributed feedback geometry with double-metal waveguides. By carefully designing the grating structures and optimizing the fabrication process, we achieve third-order distributed feedback terahertz QCL with quasi-single-longitudinal mode operation and single lobe far-field beam pattern with low beam divergence in both vertical and horizontal directions. The effect of grating duty cycle on the far-field beam divergence is systematically studied theoretically and experimentally. By the simulation, we finally achieve the divergence angle of 1213 for a third-order distributed feedback laser with a grating duty cycle of 12% that results in an effective refractive index close to 3. The experimental results show good agreement with the simulation. There is still room to further reduce the beam divergence of third-order distributed feedback terahertz QCL by improve the accuracy of the simulation and the fabrication.

半導体プロセスのCMP技術

半導体プロセスのCMP技術

Effect of tetramethylammonium hydroxide/isopropyl alcohol wet etching on geometry and surface roughness of silicon nanowires fabricated by AFM lithography.

The optimization of etchant parameters in wet etching plays an important role in the fabrication of semiconductor devices. Wet etching of tetramethylammonium hydroxide (TMAH)/isopropyl alcohol (IPA) on silicon nanowires fabricated by AFM lithography is studied herein. TMAH (25 wt %) with different IPA concentrations (0, 10, 20, and 30 vol %) and etching time durations (30, 40, and 50 s) were investigated. The relationships between etching depth and width, and etching rate and surface roughness of silicon nanowires were characterized in detail using atomic force microscopy (AFM). The obtained results indicate that increased IPA concentration in TMAH produced greater width of the silicon nanowires with a smooth surface. It was also observed that the use of a longer etching time causes more unmasked silicon layers to be removed. Importantly, throughout this study, wet etching with optimized parameters can be applied in the design of the devices with excellent performance for many applications.

Photosensitivity of InZnO thin-film transistors using a solution process

Oxide semiconductor devices play a role in both switches and photo-sensors in interactive displays. During the fabrication of oxide semiconductor devices, the sol-gel solution process that is used to form an oxide semiconductor has various merits, including its simplicity and low cost as well as its good composition controllability. Here, we present the photosensitivity characteristics of an oxide photo thin-film transistor (TFT) created using the InZnO (IZO) sol-gel process. Upon exposure to light, photocurrent (Iphoto) in the negative gate bias regime is significantly increased with a negligible threshold voltage shift. The photosensitivity is modulated by geometrical factors and by the IZO material composition. We observed a significant effect of the channel thickness and IZO composition on the photosensitivity, which was attributed to the screening effect of optically ionized oxygen vacancies (Vo++). In particular, the optimized bi-layered oxide photo-TFT presents a good Iphoto/Idark photosensitivity value of 3 × 104 and a subthreshold slope of 0.96 V/decade. In addition, the persistent photoconductivity of the oxide photo-TFT was removed by applying positive gate voltage, resulting in good high-speed operation. These results taken together demonstrate that the IZO photo-TFT produced by the sol-gel process can be workable when applied to interactive displays.

Microwave annealing, a low-thermal-budget process for dopant activation in phosphorus-implanted MOSFET devices

In this work, we investigated a low-thermal-budget dopant activation process based on microwave annealing (MWA) of phosphorus ions implanted by plasma doping and compared the proposed technique with the conventional furnace annealing and the rapid thermal annealing processes. We fabricated p-n junction diodes and metal-oxide-semiconductor field-effect transistors (MOSFETs) on silicon and silicon-on-insulator substrates, respectively, in order to examine the dopant activation resulting from MWA. The investigated low-thermal-budget MWA technique proved effective for implanted dopant atom activation and diffusion suppression. In addition, a good interface property between the gate oxide and the silicon channel was achieved. Thus, low-thermal-budget MWA is a promising and effective method for the fabrication of highly-integrated semiconductor devices.

Superconformal Film Growth: Challenges and Opportunities

State of the art manufacturing of semiconductor devices involves electrodeposition of copper for device wiring and more recently for through-silicon-vias (TSVs). The process depends on the use of electrolyte additives that affect the local deposition rate thereby resulting in superconformal, or bottom–up “superfilling” of trenches and vias. In the case of Damascene processing of submicron features the deposition process is explained by the recently developed curvature enhanced accelerator coverage (CEAC) mechanism. The model stipulates that 1.) the growth velocity is proportional to the local accelerator, or catalyst, surface coverage and 2.) the catalyst remains segregated at the metal/electrolyte interface during copper deposition. For growth on non-planar geometries this leads to enrichment of the catalyst on advancing concave surfaces and dilution on advancing convex sections; thereby giving rise to bottom-up superfilling of recessed surface features such as trenches and vias. In the case of larger features other avenues for feature filling become available that will be outlined in some detail. Despite the success of these superconformal growth processes much remains to be known concerning the detailed molecular nature of the competitive co-adsorption processes involved in both the suppression and acceleration of the metal deposition reaction. The application of in situ surface science tools such as in situ STM and SEIRAS towards a better understanding of the additive interaction will also be detailed. Finally, the talk will conclude with an overview of the current understanding of additive adsorption, consumption and/or deactivation dynamics relevant to superfilling and microstructural evolution in both Damascene and TSV Cu processing.

Device fabrication, characterization, and thermal neutron detection response of LiZnP and LiZnAs semiconductor devices

Nowotny-Juza compounds continue to be explored as candidates for solid-state neutron detectors. Such a device would have greater efficiency, in a compact form, than present day gas-filled 3He and 10BF3 detectors. The 6Li(n,t)4He reaction yields a total Q-value of 4.78MeV, larger than 10B, an energy easily identified above background radiations. Hence, devices fabricated from semiconductor compounds having either natural Li (nominally 7.5% 6Li) or enriched 6Li (usually 95% 6Li) as constituent atoms may provide a material for compact high efficiency neutron detectors. Starting material was synthesized by preparing equimolar portions of Li, Zn, and As sealed under vacuum (10−6Torr) in quartz ampoules lined with boron nitride and subsequently reacted in a compounding furnace [1]. The raw synthesized material indicated the presence high impurity levels (material and electrical property characterizations). A static vacuum sublimation in quartz was performed to help purify the synthesized material [2,3]. Bulk crystalline samples were grown from the purified material [4,5]. Samples were cut using a diamond wire saw, and processed into devices. Bulk resistivity was determined from I–V curve measurements, ranging from 106–1011Ω cm. Devices were characterized for sensitivity to 5.48MeV alpha particles, 337nm laser light, and neutron sensitivity in a thermal neutron diffracted beam at the Kansas State University TRIGA Mark II nuclear reactor. Thermal neutron reaction product charge induction was measured with a LiZnP device, and the reaction product spectral response was observed.

Large Bandgap Shrinkage from Doping and Dielectric Interface in Semiconducting Carbon Nanotubes.

The bandgap of a semiconductor is one of its most important electronic properties. It is often considered to be a fixed property of the semiconductor. As the dimensions of semiconductors reduce, however, many-body effects become dominant. Here, we show that doping and dielectric, two critical features of semiconductor device manufacturing, can dramatically shrink (renormalize) the bandgap. We demonstrate this in quasi-one-dimensional semiconducting carbon nanotubes. Specifically, we use a four-gated device, configured as a p-n diode, to investigate the fundamental electronic structure of individual, partially supported nanotubes of varying diameter. The four-gated construction allows us to combine both electrical and optical spectroscopic techniques to measure the bandgap over a wide doping range.

Optimization of fluid characteristics of 2D materials for inkjet printing

ABSTRACT2D materials have shown to be the next step in semiconductor use and device manufacturing that can allow us to reduce the size of most electronics. One of the novel ways to obtain 2D materials is through liquid exfoliation, in which these materials can be obtained by dispersing the smallest possible particles in different solvents. Once obtained, the solutions can be used to manufacture devices via different processes, one of which is inkjet printing. This process relies in selecting “jettable” fluids, which need to have the necessary combination of viscosity and surface energy or “wettability”. In this work we have modified the viscosities and surface energies of five solvents: IPA (Isopropanol), NMP (N-methyl – 2 pyrrolidone), DMA (Dimethylacetamide), DMF (Dimethylformamide) and a mixture of Cyclohexanone / Terpineol 7:3. We have found an avenue to tailor the viscosity of these solvents though the addition of Ethyl Cellulose (EC), where the viscosity has been increased by up to 15 times at an EC concentration of 6%. For inkjet printing, ideally a viscosity of 4 – 10 cP is recommended, which we have been able to achieve with all of the solvents studied. It has been found that the different solvents present different susceptibilities to the EC addition, with DMA and DMF being the least sensitive to the EC addition. We have also studied the change in the drop dynamics and interactions of the 2D solutions with the substrate. Through this analysis we have found solvents that appear to be attractive for inkjet printing of MoS2 and graphite.

On a reduction in cracking upon the growth of AlN on Si substrates by hydride vapor-phase epitaxy

The main problem of the epitaxial growth of thick AlN layers on a Si substrate consists in the formation of cracks, which complicates the application of structures of this kind in the fabrication of semiconductor devices. The possibility of obtaining crack-free AlN layers with a thickness exceeding 1 μm and a mirror- smooth surface by hydride vapor-phase epitaxy is demonstrated. The properties of the layers are studied by X-diffraction analysis, optical and scanning electron microscopy, and Raman spectroscopy.

Simulation of a Nanoscale SOI TG n-FinFET

The objective of this work is to study the electrical characteristics of a nanoscale SOI Tri-Gate n-channel fin field-effect transistor (FinFET) structure with 8 nm gate length using Semiconductor TCAD tools. ATLASTM tools are computer programs which allow for the creation, fabrication, and simulation of semiconductor devices in three dimensions with different models under consideration. The drain current, transconductance, threshold voltage, subthreshold slope, leakage current, drain induced barrier lowering, and IOn/IOff current ratio are analyzed in the various biasing configuration. In addition, FinFET device with a high value of gate dielectric constant exhibits much better performance compared to the Si3N4 dielectric material, which is desirable for high performance low-power/low-voltage applications. It is found that increasing the high-k value was beneficial in reducing the subthreshold slope, DIBL, and leakage current. General Terms Integrated Circuit, VLSI, FinFET Device Modeling.