Low Power Operation Research Articles

Alignment layer and helix controlled unconventional operational switching in ferroelectric liquid crystal

Substrate interface driven helical unwinding led dynamical switching is observed and analysed for the low voltage operation switching of ferroelectric liquid crystal (FLC). The surface driven FLC molecules force the bulk molecules to switch the sample cell device at very low voltage as compared to conventional cells. It has been shown in the present investigation using three FLC materials that the surface anchoring of the FLC molecules and the thickness of the cell play a primary role for such devices because these conditions contrive the surface interface particle helical unwinding which is very essential for the low power switching. However, P s, helical pitch value, and the dielectric strength parameters of the FLC materials are also taken into account for the analysis of bulk switching assisted by interfacial switching. Dielectric and electro-optics investigation has proven that once the relaxation process associated with the interface is confirmed by dielectric spectra then only, the low power operation is observed in the sample which is interesting for fundamental and potential electro optical devices application.

Interlayer engineering for enhanced ferroelectric tunnel junction operations in HfO x -based metal-ferroelectric-insulator-semiconductor stack

Ferroelectric tunnel junction (FTJ) has been considered as a promising candidate for next-generation memory devices due to its non-destructive and low power operations. In this article, we demonstrate the interlayer (IL) engineering in the FTJs to boost device performances. Through the analysis on the material and electrical characteristics of the fabricated FTJs with engineered IL stacks, it is clearly found that the insertion of an Al2O3 layer between the SiO2 insulator and the pure-HfO x FE improves the read disturbance (2V c = 2.2 V increased), the endurance characteristics (tenfold improvement), and the cell-to-cell TER variation simultaneously without the degradation of the ferroelectricity (less than 5%) and the polarization switching speeds through grain size modulation. Based on these investigations, the guidelines of IL engineering for low power ferroelectric devices were provided to obtain stable and fast memory operations.

An IoT-Based System for Monitoring the Health of Guyed Towers in Overhead Power Lines.

The collapse of overhead power line guyed towers is one of the leading causes of power grid failures, subjecting electricity companies to pay considerable, high-value fines. In this way, the current work proposes a novel and complete framework for the remote monitoring of mechanical stresses in guyed towers. The framework method comprises a mesh network for data forwarding and neural networks to improve the performance of Low-Power and Lossy Networks. The method also considers the use of multiple sensors in the sensor fusion technique. As a result, the risk of collapse of guyed cable towers reduces, due to the remote monitoring and preventive actions promoted by the framework. Furthermore, the proposed method uses multiple input variable fusions, such as accelerometers and tension sensors, to estimate the tower’s displacement. These estimations help address the structural health of the tower against failures (i.e., loosening of the stay cables, displacement, and vibrations) that can cause catastrophic events, such as tower collapse or even cable rupture.

Low Power Memory System Design Using Power Gated SRAM Cell

Static Random-Access Memory (SRAM) is widely used in cache memory, microprocessors, general computing applications and electronic circuits involving ASIC, FPGA and CPLD. The most commonly used SRAM is the 6T SRAM. However, it incurs higher power consumption and degraded signal to noise margin (SNM) during write and read operations. To overcome these shortcomings, a single ended power gated 11T SRAM for low power operation is proposed. The power consumption reduction is achieved using power gating through virtual VSS (VVSS) signal and transmission gates. Due to the introduction of transmission gates, memory cells realize enhanced write margin characteristics as compared to existing technologies. The proposed cell realizes 33.33% lower power consumption and 50% improvement in read SNM as compared to existing SRAM technologies. To study the impact of technology scaling on our proposed design, the work is carried out in Cadence Virtuoso® tool using both 180nm CMOS technology and BPTM 32nm FinFET technology.

Atomically Thin, Optically Isotropic Films with 3D Nanotopography.

Flat optics aims for the on-chip miniaturization of optical systems for high-speed and low-power operation, with integration of thin and lightweight components. Here, we present atomically thin yet optically isotropic films realized by using three-dimensional (3D) topographic reconstruction of anisotropic two-dimensional (2D) films to balance the out-of-plane and in-plane optical responses on the subwavelength scale. We achieve this by conformal growth of monolayer transition metal dichalcogenide (TMD) films on nanodome-structured substrates. The resulting films show an order-of-magnitude increase in the out-of-plane susceptibility for enhanced angular performance, displaying polarization isotropy in the off-axis absorption, as well as improved photoluminescence emission profiles, compared to their flat-film counterparts. We further show that such 3D geometric programming of optical properties is applicable to different TMD materials, offering spectral generalization over for the entire visible range. Our approach presents a powerful platform for advancing the development of atomically thin flat optics with custom-designed light–matter interactions.

An Ultra-Low-Power, Self-Start-Up DC-DC Boost Converter for Self-Powered IoT Node

This paper presents an ultra-low-power boost converter for self-powered IoT applications to self-start and power-up IoT devices from scratch without any requirement of an external start-up. The proposed converter and its clock generator operate in sub-threshold utilizing bulk-driven technique for low-power operation. The bulk-driven technique improves charge transfer switches for effective switching using auxiliary transistors. This approach enables a MOSFET to operate on supplies lower than its threshold voltage with a significant reduction in the reverse charge transfer and switching loss while increasing the voltage conversion efficiency and output voltage. To validate the performance of the proposed architecture, the post-layout simulation is carried out in standard CMOS 0.18[Formula: see text][Formula: see text]m technology. Under low-voltage supply of 0.4[Formula: see text]V, the simulated transient output voltage takes 110[Formula: see text][Formula: see text]s to reach 1.92[Formula: see text]V with 0.15[Formula: see text] output voltage ripple, while consuming the power of 772[Formula: see text]nW.

Impact of the nucleation of conducting clusters on the retention of memristors: A self-consistent phase-field computational study

In recent years, resistive RAM often referred to as a memristor is actively pursued as a replacement for non-volatile-flash memory due to its superior characteristics such as high density, scalability, low power operation, high endurance, and fast operating speed. However, one of the challenges that need to be overcome is the loss of retention for both ON- and OFF-states—the retention loss. While various models are proposed to explain the retention loss in memristors consisting of a switching layer, in this paper, we propose that the nucleation of conducting clusters in the switching layer acts as a potential root cause for the retention loss. The nucleation results from a localized electric-field produced intermittently during cyclic switching operations. We use the phase-field method to illustrate how the nucleation of conducting clusters gives rise to the retention loss. Our results suggest that the degree at which the retention loss arises is linked to the number of cyclic switching operations since the probability at which nucleation centers form increases with the number of cycle switching operations, which is consistent with a range of experimental findings previously reported.

Performance Considerations for Quantum Radar

Quantum radar takes advantage of quantum correlations. Detection concepts have been devised to facilitate a gain which exceeds the gain of a classical radar. Quantum radar can use squeezed microwave states and benefit from the photon entanglement. Low power operation is required for this benefit. In the contribution we investigate aspects for modeling of quantum radar relevant to the quantum radar's performance.

Ultrafast Silicon MZI Optical Switch With Periodic Electrodes and Integrated Heat Sink

The compact, high-speed, low-power consumption Mach-Zehnder interferometer (MZI)-type optical switch using thermo-optical effect is a key device in future optical integrated circuits. In this study, we achieved ultra-high-speed switching operation of 0.4 μs and low electrical power operation of 23 mW with a small device footprint by loading an asymmetric doped MZI structure and an integrated heat sink. This optical switch can be fabricated in the standard manufacturing process of silicon photonic devices, has high practicality and will be a useful tool in various optical integrated circuits.

Energy harvesting effect on prolonging low-power lossy networks lifespan

Low-power lossy networks performance relies heavily on the wireless node battery status. Furthermore, Routing Protocol for Low-Power and Lossy Network routing protocol was not optimally designed with sustainable energy consumption in mind to suit these networks. Prolonging the lifespan of these networks is of utmost priority. This article introduces a solar energy harvesting module to power energy-constrained network devices and quantifies the effect of using harvested energy on prolonging their network lifetime when Routing Protocol for Low-Power and Lossy Network routing protocol is used. Simulation of the new developed module is conducted in three different scenarios using Contiki Cooja simulator sporting Zolertia Z1 motes. Furthermore, the harvested energy used was fed from a Cooja-based Simulation model of actual PV supercapacitor circuit design. All battery levels were set to 1% of their total capacity for all nodes in the network to speed up observing the energy harvesting effect. The performance evaluation results showed that the network with no-energy harvesting operated for time duration of 4:08:04 time units (i.e. hour:minute:second) with a dramatic decrease in connection between nodes in the network. However, the same network, when using the harvested energy to back up the battery operation, lasted for 6:40:01 in time units with improved connectivity, a total extended network lifetime of 2:31:97-time units. Furthermore, for the Routing Protocol for Low-Power and Lossy Network routing metrics, OF0 outperformed ETX in term of throughput, packet delivery ratio, energy consumption, and network connectivity. Results indicate that the developed harvested energy module fits perfectly for any Cooja-based simulation and mimics actual photovoltaic-based supercapacitor battery. It should also help researchers introduce and quantify accurately new energy consumption-based routing metrics for Routing Protocol for Low-Power and Lossy Network.

A Smart Archive Box for Museum Artifact Monitoring Using Battery-Less Temperature and Humidity Sensing.

For the first time, this paper reports a smart museum archive box that features a fully integrated wireless powered temperature and humidity sensor. The smart archive box has been specifically developed for microclimate environmental monitoring of stored museum artifacts in cultural heritage applications. The developed sensor does not require a battery and is wirelessly powered using Near Field Communications (NFC). The proposed solution enables a convenient means for wireless sensing with the operator by simply placing a standard smartphone in close proximity to the cardboard archive box. Wireless sensing capability has the advantage of enabling long-term environmental monitoring of the contents of the archive box without having to move and open the box for reading or battery replacement. This contributes to a sustainable preventive conservation strategy and avoids the risk of exposing the contents to the external environment, which may result in degradation of the stored artifacts. In this work, a low-cost and fully integrated NFC sensor has been successfully developed and demonstrated. The developed sensor is capable of wirelessly measuring temperature and relative humidity with a mean error of 0.37 °C and ±0.35%, respectively. The design has also been optimized for low power operation with a measured peak DC power consumption of 900 μW while yielding a 4.5 cm wireless communication range. The power consumption of the NFC sensor is one of the lowest found in the literature. To the author’s knowledge, the NFC sensor proposed in this paper is the first reporting of a smart archive box that is wirelessly powered and uniquely integrated within a cardboard archive box.

Probing Ferrimagnetic Semiconductor with Enhanced Negative Magnetoresistance: 2D Chromium Sulfide

AbstractMagnetic 2D materials have emerged as a great interest in spintronics due to atomic thickness scaling, low energy switching, and ease in the manipulation of spins. This report demonstrates a facile, bottom‐up, chemical vapor deposition approach for non‐van der Waals (non‐vdWs), 2D chromium (III) sulfide (Cr2S3) with c‐axis orientation, out‐of‐plane magnetic anisotropy (easy axis), and ferrimagnetic ordering. Importantly, the anisotropic magnetic saturation and resistivity of 10.23 mΩ cm reveal a narrow bandgap ferrimagnetism in Cr2S3 (∆EActivation ≈ 22 meV and Eg ≈ 40 meV). The prototype lateral spin‐channel Al/Cr2S3/Al devices exhibit a negative magnetoresistance of ≈25% and ≈15% at 100 K (below Néel temperature) for few‐layer (≈8 nm) and thin‐film (≈50 nm) device structures, respectively, owing to itinerant ferrimagnetism of Cr2S3. The magnetic field‐induced spin polaron formations are quite resilient and enhance the field‐dependent carrier conduction, making it greatly useful for negative magnetoresistance operation. These prototype Al/Cr2S3/Al structures have demonstrated a low power (≈2 µW for 8 µm channel at 10 µA current) operation with a negative field‐dependent resistance coefficient (rM) of ≈−5 × 10−4 Oe−1. The computed rM magnitude is tenfold higher than the bulk Cr2S3. This study identifies the potential of non‐vdW Cr2S3 toward new and robust 2D‐based spintronic applications.

Design of an Efficient Parallel Comparator Architecture for Low Power Delay Product

A binary comparator architecture is proposed in this work for static logic to achieve both low-power and high-performance operations. It also presents a detailed timing performance and power analysis of various state-of-the-art comparator designs. The main advantages of this design are its high speed and power efficiency maintained over a wide range of operands size, which is useful at low-input data activity environments. The proposed circuit design uses minimum fan-in and fan-out logic gates for achieving high speed and low power dissipation. Utilizing a 2-bit binary comparator circuit with minimum fan-in and fan-out of logic gates (NAND-NOR), the architecture of a parallel binary comparator is proposed for higher input operands by using a low radix multiplexer and priority encoder. Further, to decrease the size of the multiplexer and priority encoder by two times, a general architecture is also proposed by using a 4-bit binary comparator to reduce its complexity. The proposed circuits are optimized in terms of the power consumption and delay, which are due to low load capacitance, low leakages, and reduced dynamic power dissipation. Each of the proposed circuits has its own merits in terms of speed, power consumption, Power-Delay Product (PDP). Its synthesis is done on 180 nm as well as 90 nm CMOS technology using the Cadence tool. The physical layout of the proposed architecture using a 90 nm CMOS process (GPDK process) is also obtained.

Design of a Robust Memristive Spiking Neuromorphic System with Unsupervised Learning in Hardware

Spiking neural networks (SNN) offer a power efficient, biologically plausible learning paradigm by encoding information into spikes. The discovery of the memristor has accelerated the progress of spiking neuromorphic systems, as the intrinsic plasticity of the device makes it an ideal candidate to mimic a biological synapse. Despite providing a nanoscale form factor, non-volatility, and low-power operation, memristors suffer from device-level non-idealities, which impact system-level performance. To address these issues, this article presents a memristive crossbar-based neuromorphic system using unsupervised learning with twin-memristor synapses, fully digital pulse width modulated spike-timing-dependent plasticity, and homeostasis neurons. The implemented single-layer SNN was applied to a pattern-recognition task of classifying handwritten-digits. The performance of the system was analyzed by varying design parameters such as number of training epochs, neurons, and capacitors. Furthermore, the impact of memristor device non-idealities, such as device-switching mismatch, aging, failure, and process variations, were investigated and the resilience of the proposed system was demonstrated.

Constant delay systolic binary counter with variable size cellular automaton based prescaler

An One-Dimension (1D) Cellular Automaton (CA) is studied as a generator for the radix-2 sequence, presenting suitable characteristics for the design of a fast and constant delay synchronous digital counter. The main contribution of this work is the proposal of a new type of synchronous digital counters including a CA-based prescaler and consecutive counting modules of various configurations (in terms of bitlength, speed and area requirements) to result in a modular and systolic counting structure with the minimum redundant hardware and low-power operation. It is the first time that a thorough exploration of the 1D CA rule 102 is offered and considered as the prescaler of a systolic counter of heterogeneous modules in size, achieving the desired constant delay characteristic with low area/power penalty. The proposed counter, compared to hard Intellectual Property (IP) cores, presents up to 90% enhancement of speed for 9.37%–33.0% area penalty for reconfigurable technologies.

A 17.5dB wide-dynamic range high-efficiency RF-to-DC power converter for wireless energy harvesting

ABSTRACT A novel reconfigurable RF-to-DC power converter is proposed for wireless energy harvesting. The proposed RF rectifier employs low-threshold transistors with cross-coupled configuration to enhance the flow of the forward current to the load at low input RF power and adaptive stacking diodes to reduce the leakage current by lowering the driving voltage of the rectifying PMOS transistors at high input RF power. The proposed rectifier utilises the body biasing technique to modulate the threshold voltage and minimises the leakage current of the feedback diodes. The proposed novel techniques improve efficiency and extend the dynamic range. The prototype is implemented in a 65 nm CMOS technology and occupies an active area of 0.0148 mm2. The proposed rectifier achieves a peak power conversion efficiency (PCE) of 76% with a load of a 100-KΩ load at the industrial, scientific, and medical band 433 MHz, and the achieved sensitivity of the rectifier is −18.5 dBm for 1 V DC output voltage. The proposed rectifier offers PCE at −35 dBm of 45.6%, which is the best low-power performance. Compared to the state-of-the-art rectifiers, the proposed design achieves an excellent wide-dynamic range of 17.5 dB, which is ten times better than the conventional cross-coupled rectifier.

High selectivity and sharp roll-off filtenna array for Ku-band application

ABSTRACT A (1 × 2) filtenna array inspired by an inter-digital-based bandpass filter is presented in this paper for simultaneous radiation and filtration. The feed line of the proposed antenna array resonating at 14 GHz with fractional bandwidth of 5.72% is modified in such a way that it acts like an inter-digital-based bandpass filter. The equivalent lumped circuit model of the proposed structure is analysed and detail synthesis procedure is presented. To study the impact of dimensional variations on the performance of proposed filtenna array, various parametric studies of filtenna and corresponding antenna array are performed and compared. The design strategy involves (N-1) filter circuits for realising a (1 × N) element filtenna array. The proposed array exhibits advantageous features such as low circuit complexity, compact size and low operational power over other reported filtenna arrays. The presented filtenna possesses fractional bandwidth and peak gain of 3.85% and 8.14 dB respectively at resonating frequency of 14 GHz, which covers the standards of Ku-band. The physical size of the filtenna array in terms of free space wave length is 1.96λ0 × 1.96λ0 × 0.073λ0 at 14 GHz. The radiation patterns are omni-directional in E-plane and nearly omni-directional in nature at H-plane at resonance frequency of 14 GHz.

Memristor-Based Variation-Enabled Differentially Private Learning Systems for Edge Computing in IoT

Edge artificial intelligence (AI) achieves real-time local data analysis for IoT systems, enabling low-power and high-speed operation, but comes with privacy-preserving requirements. The memristor-based computing system is a promising solution for edge AI, but it needs a low-cost privacy protection mechanism due to limited resources. In this article, we propose a noise distribution normalization (NDN) method to add Gaussian distributed noise through hardware implementation, thereby achieving differential privacy in edge AI. Instead of using traditional algorithmic noise-insertion methods, we take advantage of inherent cycle-to-cycle variations of memristors during the weight-update process as the noise source, which does not incur extra software or hardware overhead. In one case study, the proposed method realizes ultralow-cost differentially private stochastic gradient descent (DP-SGD) for edge AI in IoT systems, achieving a 3.5%–15.5% average recognition accuracy improvement under different noise levels, as compared with a baseline mechanism.

Patch-Type Vibration Visualization (PVV) Sensor System Based on Triboelectric Effect.

Self-powered wireless sensor systems have emerged as an important topic for condition monitoring in nuclear power plants. However, commercial wireless sensor systems still cannot be fully self-sustainable due to the high power consumption caused by excessive signal processing in a mini-electronic computing system. In this sense, it is essential not only to integrate the sensor system with energy-harvesting devices but also to develop simple data processing methods for low power schemes. In this paper, we report a patch-type vibration visualization (PVV) sensor system based on the triboelectric effect and a visualization technique for self-sustainable operation. The PVV sensor system composed of a polyethylene terephthalate (PET)/Al/LCD screen directly converts the triboelectric signal into an informative black pattern on the LCD screen without excessive signal processing, enabling extremely low power operation. In addition, a proposed image processing method reconverts the black patterns to frequency and acceleration values through a remote-control camera. With these simple signal-to-pattern conversion and pattern-to-data reconversion techniques, a vibration visualization sensor network has successfully been demonstrated.

Voltage-Gate-Assisted Spin-Orbit-Torque Magnetic Random-Access Memory for High-Density and Low-Power Embedded Applications

Voltage-gate assisted spin-orbit torque (VGSOT) writing scheme combines the advantages from voltage control of magnetic anisotropy (VCMA) and spin-orbit torque (SOT) effects, enabling multiple benefits for magnetic random access memory (MRAM) applications. In this work, we give a complete description of VGSOT writing properties on perpendicular magnetic tunnel junction (pMTJ) devices, and we propose a detailed methodology for its electrical characterization. The impact of gate assistance on the SOT switching characteristics are investigated using electrical pulses down to 400ps. The VCMA coefficient ({\xi}) extracted from current switching scheme is found to be the same as that from the magnetic field switch method, which is in the order of 15fJ/Vm for the 80nm to 150nm devices. Moreover, as expected from the pure electronic VCMA effect, {\xi} is revealed to be independent of the writing speed and gate length. We observe that SOT switching current characteristics are modified linearly with gate voltage (V_g), similar as for the magnetic properties. We interpret this linear behavior as the direct modification of perpendicular magnetic anisotropy (PMA) and nucleation energy induced by VCMA. At V_g = 1V, the SOT write current is decreased by 25%, corresponding to a 45% reduction in total energy down to 30fJ/bit at 400ps speed for the 80nm devices used in this study. Further, the device-scaling criteria are proposed, and we reveal that VGSOT scheme is of great interest as it can mitigate the complex material requirements of achieving high SOT and VCMA parameters for scaled MTJs. Finally, how that VGSOT-MRAM can enable high-density arrays close to two terminal geometries, with high-speed performance and low-power operation, showing great potential for embedded memories as well as in-memory computing applications at advanced technology nodes.