Low Power Operation Research Articles

(Invited) SiGe/SOI System: Mechanisms of Condensation and Strain Relaxation

Silicon-Germanium strain engineering has been used for more than two decades in silicon based devices and has contributed to the scaling down of a transistor’s size and to significant improvements in device performance. However, while conventional silicon-germanium based electronics has experienced rapid and steady growth, thanks to this continuous miniaturization of transistors, this trend cannot continue indefinitely. Industry has already moved to alternate methods such as FinFET devices, in which a thin silicon channel is placed vertically, and the FD-SOI (FD-SGOI) design consisting of a thin film Si(SiGe) channel placed horizontally. For nodes scaled down below 28 nm, low power operation will be inherently hindered by both the imperfect interface, non-uniformity of ultra-thin films and quantum confinement effects, which increase the effective bandgap. In these devices, despite the intense research activity on the strained SiGe ultra-thin body, which accounts for a large portion of such microelectronic devices (below the 45 nm node), we still fail to properly understand the mechanisms that limit hole and electron mobilities in SGOI layers. In addition, one of the main challenges for Si based devices remains the fabrication of efficient group-IV photon sources / photon detectors compatible with the microelectronic industry, which would usefully replace the integration of III-V heterostructures on Si. The major bottleneck is that group-IV semiconductor elements have indirect bandgaps, but with possibilities of being transformed to direct bandgaps using strain engineering strategies.In this presentation, we will review the formation mechanism of Ge-rich layers on SOI by condensation at different temperatures. TEM cross-section and GPA analysis of the heterostructures will be presented. We will also report the physical and optical properties of these heterostructures. Special attention is devoted to the influence of the SiGe thickness reduction (up to few MLs), where quantum confinement is prominent in the optical properties of the layers. Raman and PL results will be presented to better explain such confinement behavior. We show that novel SGOI substrates could represent a key strategy for the fabrication of future photonic devices.

Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs

In recent years, Ge-based group-IV alloys (GeSn, SiGeSn) have received a significant amount of attention as candidates to replace Silicon for future low power and high performance nanoelectronics [1]. The interest in these materials stems primarily from the fact that, by varying the Sn-content of the alloy, it is possible to precisely tune its bandgap from indirect to direct [2], which even opens up the possibility to switch the carrier transport from larger mass low mobility L-valley electrons to the lower mass and high mobility Γ-valley electrons. Adding Si atoms into GeSn alloys enables additional strain engineering by decoupling the lattice constant from the band gap and enables the fabrication of devices to target specific applications. Ge exhibits superior hole mobility over Si and GeSn is predicted to further improve carrier mobilities for both electrons and holes, while still retaining Si CMOS compatibility [3]. In this , we present the fabrication and characterization of Ge- and GeSn-based vertical gate-all-around (GAA) nanowire (NW) p-MOSFETs. Multilayer stacks of Ge and GeSn were grown on a Ge virtual substrate (Ge-VS) using industrial CVD reactors and subsequently characterized, confirming the high quality of the alloys.On these GeSn/Ge heterostructures, vertical GAA nanowire FETs were fabricated using a top-down approach. First, nanowires were defined by electron-beam lithography and subsequently etched anisotropically using reactive ion etching (RIE). The diameter of the nanowires was reduced by digital etching, consisting of repeated combined GeOx layer formation by plasma oxidation and removal in diluted HF solution. This way nanowires with a diameter down to 20 nm and a height of 210 nm were fabricated. A two-step process was employed for gate dielectric formation to ensure a low interface trap density: (i), deposition of a thin layer of Al2O3, followed by an O2-plasma post-oxidation step; (ii) deposition of a HfO2 dielectric layer to reach the required EOT (equivalent oxide thickness). TiN deposited by sputtering forms the gate metal. Planarization and isotropic dry etching were performed to remove the TiN on the top of the nanowire. After a second planarization step, NiGe-contacts were formed on the exposed top nanowire by Ni-deposition followed by a forming-gas annealing step. Finally, metal contacts for gate and source/drain were added.The resulting Ge-NW-pMOSFETs exhibit high electrical performances. A low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering (DIBL) of 35 mV/V and an I on/I off-ratio of 2.1×106 were measured for nanowires with a diameter of 20 nm. For 65 nm NWs, the I on/I off-ratio improves, which is attributed to the decreased contact resistance on top of the NWs, leading to larger on-currents. The peak transconductance for the Ge NWs reached ~190 µS/µm (V DS=-0.5 V). Adopting a GeSn/Ge-heterostructure, with GeSn on top of the nanowire used as source the device performances are strongly enhanced. The on-current I on was increased by ~32%, mostly due to the reduced contact resistivity of the smaller bandgap of GeSn compared to Ge. It was also observed that adopting GeSn alloys leads to an increase in transconductance, G max, to a respectable value of ~870 µS/µm, almost 3 times larger as reported to date for Ge NWs. Moreover, both SS and DIBL are improved by decreasing the NW diameter as a consequence of improved electrostatic gate control over the channel.These results demonstrate that the incorporation of GeSn into Ge-MOSFET technology yields a significant advantage and confirm its high potential for low-power-high-performance nanoelectronics.Fig. 1: (a) Schematic of the GAA nanowire FET based on a GeSn/Ge-heterostructure. (b) Optical image on the metallic contacts (c) Transfer curve of a Ge nanowire pFET with a diameter of 20 nm. The SS is 68 mV/dec and the DIBL is 35 mV/V. (d) Transfer curves of Ge0.92Sn0.08/Ge nanowire pFETs with a diameter of 65 nm and different EOTs. Acknowledgments The authors acknowledge support from the German BMBF project “SiGeSn NanoFETs”.

A bidirectional three-level interleaved DC-DC converter for an electric vehicle charging station operating in a wide range of battery currents and voltages

Charging an Electrical Vehicle (EV) is a process dependent on the specs of their battery in each car with the charger being custom designed. This means that designing the converter for a general EV charging station is very challenging because it must accommodate a wide variety of currents/voltages/powers whilst maintaining a high conversion efficiency and low cost/size. To minimise the size of the magnetics, this paper proposes the use of both multilevel and interleaved technologies to easily support load voltage/current/power scale up. A 3-level flying capacitor converter topology usually deployed in DC/AC application is proposed to be integrated in a 2-channel interleaved implementation where each bidirectional three-level interleaved (B3LI) converter leg switches only half the load current and half the main DC source voltage. The system controller is equipped with phase current balancing and capacitor voltage equalisation control to maintain the system stability along with phase shedding control to reduce losses during low power operation. Simulations are implemented in PLECS software to validate the expected performance and operation of the proposed converter system.

Medium-Temperature-Oxidized GeOx Resistive-Switching Random-Access Memory and Its Applicability in Processing-in-Memory Computing

Processing-in-memory (PIM) is emerging as a new computing paradigm to replace the existing von Neumann computer architecture for data-intensive processing. For the higher end-user mobility, low-power operation capability is more increasingly required and components need to be renovated to make a way out of the conventional software-driven artificial intelligence. In this work, we investigate the hardware performances of PIM architecture that can be presumably constructed by resistive-switching random-access memory (ReRAM) synapse fabricated with a relatively larger thermal budget in the full Si processing compatibility. By introducing a medium-temperature oxidation in which the sputtered Ge atoms are oxidized at a relatively higher temperature compared with the ReRAM devices fabricated by physical vapor deposition at room temperature, higher device reliability has been acquired. Based on the empirically obtained device parameters, a PIM architecture has been conceived and a system-level evaluations have been performed in this work. Considerations include the cycle-to-cycle variation in the GeOx ReRAM synapse, analog-to-digital converter resolution, synaptic array size, and interconnect latency for the system-level evaluation with the Canadian Institute for Advance Research-10 dataset. A fully Si processing-compatible and robust ReRAM synapse and its applicability for PIM are demonstrated.Graphical

Design and Implementation of Low-Cost Distributed Tabletop Magnetic Particle Imaging System

Magnetic particle imaging (MPI) is a novel tomography model that mainly benefits from the nonlinear magnetization response of magnetic nanoparticles under a dramatically changing magnetic field. Low-cost and compact system construction is beneficial to the application of education, biomedical research, preclinical and clinical medicine. Conversely, many aspects of the production cost, infrastructure requirements, and distributed measurements can be prohibitively expensive for them. In this article, a low-cost, compact tabletop MPI scanner based on a field-programmable gate array (FPGA) framework with an Advanced RISC Machine (ARM) cores was proposed to address these issues. First, the proposed low-cost MPI scanner was realized by substituting discrete elements, which is affordable to cover the most economically underdeveloped regions. Besides, the ARM cores embedded in the FPGA framework which has the inherent advantages of low-power operation, are exploited to execute high-power real-time data transmission tasks instead of conventional X86. And a customized tabletop MPI system was constructed via the proposed architecture for advanced distributed MPI research. Simulative vessel experiments with commercial superparamagnetic nanoparticles (SPIONs) have been performed in the proposed system by vessel phantoms. The experimental images showed that the proposed system could achieved an image resolution of approximately 2 mm, which can distinguish spatial locations of brain veins (2–4 mm in diameter). Moreover, the experiment of distributed transmission showed that the proposed system could perform the collection and transmission of distributed particle signals based on the inherent user datagram protocol (UDP) network transmission protocol with an average round trip time (RTT) of 28.044 ms. Hence, the proposed system has the potential to apply the network cloud to get distributed biomedical information for remote education or diagnosis.

Development of a High-Reliability Vacuum Arc Thruster System

Current vacuum arc thruster systems show insufficient reliability in the low-power () operation mode, which is required for CubeSat propulsion systems. Typically, the failure of the whole thruster system is caused by the failure of the arc ignition system. The reasons for this are deposition of a conducting coating on the insulator surface and geometry changes of the cathode. In this work, a highly reliable vacuum arc thruster system for electric propulsion of small satellite systems (for example, CubeSats) is presented. It is able to reach more than 10 million pulses while keeping the trigger voltage below 3 kV, which is one order of magnitude higher than those of previously published results. The system includes a novel thruster head design in combination with a newly developed power supply system. It was tested with a variable pulse frequency from 1 to 5 Hz. The thruster uses a single titanium cathode in combination with a dual-anode design and can be easily extended with a magnetic nozzle. The combination of the geometry and the power supply creates a system that deals with the aforementioned failure mechanisms. Several long-term tests were performed to demonstrate the system’s functionality. Moreover, erosion measurements and a failure analysis were conducted.

Reliability aspects of binary vector-matrix-multiplications using ReRAM devices

Computation-in-memory using memristive devices is a promising approach to overcome the performance limitations of conventional computing architectures introduced by the von Neumann bottleneck which are also known as memory wall and power wall. It has been shown that accelerators based on memristive devices can deliver higher energy efficiencies and data throughputs when compared with conventional architectures. In the vast multitude of memristive devices, bipolar resistive switches based on the valence change mechanism (VCM) are particularly interesting due to their low power operation, non-volatility, high integration density and their CMOS compatibility. While a wide range of possible applications is considered, many of them such as artificial neural networks heavily rely on vector-matrix-multiplications (VMMs) as a mathematical operation. These VMMs are made up of large numbers of multiplication and accumulation (MAC) operations. The MAC operation can be realised using memristive devices in an analog fashion using Ohm’s law and Kirchhoff’s law. However, VCM devices exhibit a range of non-idealities, affecting the VMM performance, which in turn impacts the overall accuracy of the application. Those non-idealities can be classified into time-independent (programming variability) and time-dependent (read disturb and read noise). Additionally, peripheral circuits such as analog to digital converters can introduce errors during the digitalization. In this work, we experimentally and theoretically investigate the impact of device- and circuit-level effects on the VMM in a VCM crossbars. Our analysis shows that the variability of the low resistive state plays a key role and that reading in the RESET direction should be favored to reading in the SET direction.

A Low-Power ADPLL with Calibration-Free RO-Based Injection-Locking TDC for BLE Applications

This paper proposes a low-power all-digital phase-locked loop (ADPLL) with calibration-free ring oscillator (RO)-based injection-locking time to digital converter (TDC) for BLE applications. The RO is reused as the delay cell of TDC, and the quantization step of TDC is always tracked with the RO period; hence no calibration is needed in this architecture. We adopt RO tuning to lower the injection-locking bandwidth so as to decrease the power consumption of the injection current. Moreover, the fractional part of phase error detection is turned down in the coarse tuning of ADPLL to save power. An LC-based digital-controlled oscillator (LCDCO) with a 6.4 nH inductor and a resistive bias is used to have a low power and better phase noise performance. The ADPLL is fabricated in 40 nm CMOS with a 1 V supply and consumes 1.4 mW when it is locked. The measured phase noise is −114 dBc/Hz at 1 MHz offset. The test results show significant power saving. Thus, it can be a promising candidate for BLE applications.

Development of an Engine Power Binning Method for Characterizing PM2.5 and NOx Emissions for Off-Road Construction Equipment with DPF and SCR

Aftertreatment technologies in Tier 4 off-road engines have resulted in significant emission reductions compared to older tier engines without aftertreatments. The appropriate characterization of Tier 4 engine emissions in consideration of aftertreatment operation is important for projecting emissions and developing mitigation strategies. The current method of aggregating emissions over an entire duty cycle and averaging them by engine load has a limitation in developing emission profiles over various duty cycles of Tier 4 engines, especially at low-load operations, where aftertreatment control for NOx may not be effective. In this study, an engine power binning method was developed to characterize emissions for Tier 4 construction equipment with aftertreatment systems, especially at low-power operating conditions. This binning method was applied to real-time emissions and activity data for four different types of Tier 4 construction equipment. Results show that low-power operations (<20% engine power) are responsible for 38–60% NOx and 11–51% of PM2.5 emissions depending on the equipment types. These results underscore the need for controlling NOx emissions during low-power operations. PM2.5 EFs for non-DPF backhoes were one to two orders of magnitude greater than all the other equipment due to the lack of a DPF, despite being certified to the same PM2.5 standard. This shows the benefits of DPFs on construction equipment and that they are substantial in reducing PM2.5 emissions. Estimated emission differences between using the binning and the averaging methods were 49–86% and 16–82% for NOx and PM2.5, respectively. These differences may change once the binning method is applied to larger emission datasets obtained from real-world vocational activities.

Experimental and analytical natural circulation analysis of the Jordanian 5 MW research reactor using plate type fuel by RELAP5 MOD3.3

The 5-MWth Jordanian research reactor is an open-pool type research reactor using plate-type fuel. It is cooled by the upward natural flow at low power-operation. Natural circulation cooling is important in the safety analysis because it is the last scenario of all accidents. Therefore, studying natural circulation is important in determining the safety limits, such as the maximum allowed temperature and the minimum critical heat flux ratio of fuel. In this paper, the reactor operated at 50KW by the natural circulation to investigate its neutronics and thermal–hydraulic characteristics. Then, the results were benchmarked with RELAP5 MOD 3.3 by implementing models with and without considering the effect of heat loss through the Upper Guide Structure. As a result of this study, different models show minor differences in thermodynamic parameters and an additional safety margin. Eventually, benchmarking the results and the calculations of RELAP5 led to a reasonable agreement in both simulated models.

Cross-gain modulation-based photonic reservoir computing using low-power-consumption membrane SOA on Si.

We demonstrate photonic reservoir computing (RC) utilizing cross-gain modulation (XGM) in a membrane semiconductor optical amplifier (SOA) on a Si platform. The membrane SOA's features of small active volume and strong optical confinement enable low-power nonlinear operation of the reservoir, with 101-mW-scale power consumption and 102-µW-scale optical input power. The power consumption is about an order of magnitude lower than that of conventional SOAs that exhibit saturable nonlinearity. The XGM-based reservoir is configured by injecting a delayed feedback signal into the SOA from a direction opposite to the input signal. This configuration provides robust operation of the feedback circuit because of the phase insensitivity and the elimination of loop oscillation risk. The RC performance is evaluated via the information processing capacity (IPC) and a nonlinear benchmark task. It is revealed that the XGM-based reservoir performs strong nonlinear transformation of input time-series signals. The series of results consistently show that the membrane SOA performs RC-applicable nonlinear operations through XGM at a low power scale.

Implementing a Timing Error-Resilient and Energy-Efficient Near-Threshold Hardware Accelerator for Deep Neural Network Inference

Increasing processing requirements in the Artificial Intelligence (AI) realm has led to the emergence of domain-specific architectures for Deep Neural Network (DNN) applications. Tensor Processing Unit (TPU), a DNN accelerator by Google, has emerged as a front runner outclassing its contemporaries, CPUs and GPUs, in performance by 15×–30×. TPUs have been deployed in Google data centers to cater to the performance demands. However, a TPU’s performance enhancement is accompanied by a mammoth power consumption. In the pursuit of lowering the energy utilization, this paper proposes PREDITOR—a low-power TPU operating in the Near-Threshold Computing (NTC) realm. PREDITOR uses mathematical analysis to mitigate the undetectable timing errors by boosting the voltage of the selective multiplier-and-accumulator units at specific intervals to enhance the performance of the NTC TPU, thereby ensuring a high inference accuracy at low voltage. PREDITOR offers up to 3×–5× improved performance in comparison to the leading-edge error mitigation schemes with a minor loss in accuracy.

Discontinuous Computation Offloading for Energy-Efficient Mobile Edge Computing

We propose a novel strategy for energy-efficient dynamic computation offloading, in the context of edge-computing-aided beyond 5G networks. The goal is to minimize the energy consumption of the overall system, comprising multiple User Equipment (UE), an access point (AP), and an edge server (ES), under constraints on the end-to-end service delay and the packet error rate performance over the wireless interface. To reduce the energy consumption, we exploit low-power sleep operation modes for the users, the AP and the ES, shifting the edge computing paradigm from an always on to an always available architecture, capable of guaranteeing an on-demand target service quality with the minimum energy consumption. To this aim, we propose an online algorithm for dynamic and optimal orchestration of radio and computational resources called Discontinuous Computation Offloading (DisCO). In such a framework, end-to-end delay constraints translate into constraints on overall queueing delays, including both the communication and the computation phases of the offloading service. DisCO hinges on Lyapunov stochastic optimization, does not require any prior knowledge on the statistics of the offloading traffic or the radio channels, and satisfies the long-term performance constraints imposed by the users. Several numerical results illustrate the advantages of the proposed method.

Feasibility Study of Performance Low Capacity Hybrid Energy Power Plant System in Remote Area

<p>The fossil energy utilization for electricity<br />generation is currently starting to be limited because it is predicted<br />that the availability of fossil energy for the next few decades will<br />run out. Renewable energy is an alternative energy that can be<br />used to generate electricity. Solar power plant is one of the<br />electrical energy generators with renewable energy sources that<br />have been widely used. Solar power plant is a Distributed<br />Generator that can be applied directly to consumers and it is very<br />suitable for use in remote areas which currently still use diesel as<br />a fuel for power generation. In this research, the design of a hybrid<br />power generation system between Soalr Energy and Wind will be<br />carried out to replace the use of diesel as a source of electricity<br />generation. After the generator design is done, then the<br />performance test of the hybrid system will be carried out in order<br />to see the feasibility of the design that has been made. From the<br />test results, the results of the Hybrid Energy Generator have<br />efficiencies ranging from 10-12% where this shows that the power<br />plant system is still said to be unable to work efficiently. The<br />average amount of energy produced from this Hybrid PLT system<br />is 1,304 kWh per day. Based on the results of the economic<br />feasibility analysis, that the use of the hybrid system is able to<br />produce savings of Rp. 1,700 – Rp. 2,100/kWh per day</p>

Two-terminal Resistive-switching Memories based on Liquid AgNO3 as Artificial Synapses

The brain presents impressive characteristics, like memory retention and learning capabilities at low energy consumption, making it the most efficient computational entity known. A promising candidate for the task of mimicking the brain is a new generation of devices showing resistive switching, a process that resembles the synaptic behavior, namely the liquid-based resistive-switching memory (LRSM). Here we present a two-terminal structure that works based on a solution of silver nitrate (AgNO3) and a silver (Ag) electrode. Furthermore, since the goal is to mimic the behavior of synapses, the dynamical properties of resistive switching, endurance and data retention were studied. Low operation power was further achieved (<0.5 V, 0.1 mA). Finally, taking advantage of the liquid medium, in which the synaptic behavior occurs, a flexible device was built using microchannels in Polydimethylsiloxane (PDMS) that allowed for the harvesting of the silver nitrate and the insertion of a silver and copper electrode.

High-density neural recording system design.

Implantable medical devices capable of monitoring hundreds to thousands of electrodes have received great attention in biomedical applications for understanding of the brain function and to treat brain diseases such as epilepsy, dystonia, and Parkinson's disease. Non-invasive neural recording modalities such as fMRI and EEGs were widely used since the 1960s, but to acquire better information, invasive modalities gained popularity. Since such invasive neural recording system requires high efficiency and low power operation, they have been implemented as integrated circuits. Many techniques have been developed and applied when designing integrated high-density neural recording architecture for better performance, higher efficiency, and lower power consumption. This paper covers general knowledge of neural signals and frequently used neural recording architectures for monitoring neural activity. For neural recording architecture, various neural recording amplifier structures are covered. In addition, several neural processing techniques, which can optimize the neural recording system, are also discussed.

Speech Assistant System With Local Client and Server Devices to Guarantee Data Privacy

Users of speech assistant systems have reservations about the distributed approach of these systems. They have concerns that people might get access to the transmitted speech data or that somebody is able to access their microphone from outside. Therefore, we investigate the concept of a setup with local client and server systems. This comes along with the requirement of cost-efficient realizations of client and server. We examined a number of different cost-efficient server solutions depending on the required recognition capability of specific applications. A fairly cost-efficient solution is the use of a small computing device for recognizing a few dozens of words with a GMM-HMM based recognition. To perform a DNN-HMM based recognition, we looked at small computing devices with an integrated additional graphical processor unit (GPU). Furthermore, we investigated the use of low-cost PCs for implementing real-time versions of the Kaldi framework to allow the recognition of large vocabularies. We investigated the control of a smart home by speech as an exemplary application. For this, we designed compact client systems that can be integrated at certain places inside a room, e.g., in a standard outlet socket. Besides activating a client by a sensor that detects approaching people, the recognition of a spoken wake-up word is the usual way for activation. We developed a keyword recognition algorithm that can be implemented in the client despite its limited computing resources. The control of the whole dialogue has been integrated in our client, so that no further server is needed. In a separate study, we examined the approach of an extremely energy-efficient realization of the client system without the need of an external power supply. The approach is based on using a special microphone with an additional low-power operating mode detecting the exceeding of a preset sound level threshold only. This detection can be used to wake up the client's microcontroller and to make the microphone switch to normal operating mode. In the listening mode, the energy consumption of the microphone is so low that a client system can be active for months with an energy supply from standard batteries only.

Low-Temperature Characteristics of Nanowire Network Demultiplexer for Qubit Biasing.

In current quantum computers, most qubit control electronics are connected to the qubit chip inside the cryostat by cables at room temperature. This poses a challenge when scaling the quantum chip to an increasing number of qubits. We present a lateral nanowire network 1-to-4 demultiplexer design fabricated by selective area grown InGaAs on InP, suitable for on chip routing of DC current for qubit biasing. We have characterized the device at cryogenic temperatures, and at 40 mK the device exhibits a minimum inverse subthreshold slope of 2 mV/dec, which is encouraging for low power operation. At low drain bias, the transmission breaks up into several resonance peaks due to a rough conduction band edge; this is qualitatively explained by a simple model based on a 1D real space tight-binding nonequilibrium Green’s functions model.

A 0.061 nJ/b 10 Mbps Hybrid BF-PSK Receiver for Internet of Things Applications

This paper describes a hybrid binary frequency-phase shift keying (BF-PSK) receiver architecture designed with a technique involving both the received signal frequency and phase for low-power operation with relatively high data rate. The method enables the demodulation of the incoming signal without synchronization requirements, which reduces the design complexity and power consumption. The architecture allows programmable data rates and channel bandwidths according to application-specific needs. A novel low-noise amplifier architecture is introduced in this paper as well. The Medical Implant Communication System (MICS) band receiver was designed and fabricated in a standard 65nm CMOS technology, and the measurement results demonstrate the feasibility of this architecture. As a proof-of-concept, it operates with a 416 MHz carrier frequency at a state-of-the-art data rate for sub-milliwatt receivers of 10 Mbps, while consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$610~\mu \text{W}$ </tex-math></inline-formula> from a 1 V supply.

A Novel Design for Low-Power, High Performance and Space Efficient Address Decoder for SRAM

Abstract: We discover the optimum decoder structure for fast low-power SRAMS. The results are ideal when the decoder is designed as a binary tree without the precoder. We find that skewed circuits with self-resetting gates work well, and we explore some basic scaling algorithms for minimal delay and power in the SRAM data path. Signal oscillations on high capacitance nodes like bit lines and data lines are decreased, resulting in low power operation. Clocked voltage sense amplifiers are required for low sensing power, and accurate construction of their sense clock is required for high-speed operation. By restricting bit line and NO line swings, we examine tracking circuits to aid in the development of the sense clock and allow timed sense amplifiers. The tracking circuits successfully use a replica memory cell and a replica bit line to track the memory cell's delay throughout a wide variety of manufacturing and operating conditions. The results of two different prototypes' experiments are reported. Finally, we investigate the speed and power development trends of SRAMs as a function of size and technology, discovering that if the connection delay is negligible, the SRAM delay grows as the logarithm of its size. Wire delay becomes increasingly important for SRAMs after the fifth generation. The wire delay worsens as the process shrinks, requiring wire redesign to keep the wire delay proportionate to the gate delay. Hierarchical SRAM topologies provide enough of array space for fat Wires and may be used to control time. Throughout the procedure, the wire delay for 4Mb and smaller designs diminishes. Keywords: SRAMs, High Performance, Delay, Clock, Decoder