Low Interface Trap Density Research Articles

Electrical characteristics of high-quality sub-25-/spl Aring/ oxides grown by ultraviolet ozone exposure at low temperature

We have developed a method for controllably and reproducibly growing self-limiting ultrathin oxides with excellent electrical properties in the range /spl sim/10-25 /spl Aring/ thick at temperatures ranging from 25 to 600/spl deg/C, respectively, using an ultraviolet ozone (UVO/sub 3/) oxidation process. The self-limiting thickness depends primarily on the substrate temperature, allowing ultrathin oxide growth with precision and reproducibility using this UVO/sub 3/ process. Oxides grown by this method are comparable in electrical quality to thermal oxides, with similar leakage current densities and breakdown fields E/sub BD/>10 MV/cm. Current-voltage (I-V) analysis shows oxide thickness uniformity to within 1% from center to edge of a 4-in wafer. Capacitance-voltage (C-V) characterization of /spl sim/25 /spl Aring/ oxides shows excellent saturation behaviour, with low midgap interface trap densities and no hysteresis or dispersion.

Low interface trap density in rapid thermally annealed Al/SiNx:H/InP metal–insulator–semiconductor devices

A minimum interface trap density of 1012 eV−1 cm−2 was obtained on SiNx:H/InP metal–insulator–semiconductor structures without InP surface passivation. The SiNx:H gate insulator was obtained by the electron cyclotron resonance plasma method. This insulator was deposited in a single vacuum run and was composed of two layers with different nitrogen-to-silicon ratios. The first layer deposited onto the InP was grown with a nitrogen-to-silicon ratio of N/Si=1.55, whereas the second one was grown with a N/Si ratio of N/Si=1.43. After the insulator deposition, rapid thermal annealing of the devices was performed at a constant annealing time of 30 s. The interface trap density minimum value was obtained at an optimum annealing temperature of 500 °C. Higher annealing temperatures promote thermal degradation of the interface and a sharp increase in the trap density.

Low-Temperature Oxidation of Silicon(100) Substrates Using Atomic Oxygen

ABSTRACTLow temperature oxidation process of Si(100) substrates using atomic oxygen has been proposed. For the generation of atomic oxygen, microwave plasma remotely attached on the oxidation chamber was used. In the microwave plasma, the large amount of rare gas and a small amount of 02 gas mixture was supplied. The existence of the large amount of rare gas controls the plasma energy to some restricted values associated with the metastable states of the rare gas. Consequently, using Kr as mixed rare gas, atomic oxygen were efficiently generated instead of excited 02 molecules with any vibrational or ionized states. The oxidation kinetics of crystalline Si using this process was shown to be diffusion limiting, even if the oxide thickness was less than several nm. The activation energy of B, which is referred to as the parabolic rate constant, was found to be as low as 0.14eV In addition, lower interface trap density of 2.6 × 1011/cm2/eV at the mid gap could be achieved for the as-grown SiO2/Si(100) interface at the processing temperature of 500C.

Characterization of Pb(Zr, Ti)O3 Thin Films on Si Substrates Using MgO Intermediate Layer for Metal/Ferroelectric/Insulator/Semiconductor Field Effect Transistor Devices

Pb(Zr, Ti)O3(PZT)/MgO/Si(001) stacked structures, one of the potential components of ferroelectric-gate field effect trnsistors, have been fabricated and characterized. According to the electrical characterization of MgO/Si structures, MgO thin films prepared on Si substrates at a low growth rate showed a small leakage current of ∼10-8 A/cm2 order in an electric field of 1 MV/cm. In C-V measurements of as-grown MgO/Si interfaces, injection-type hysteresis was observed because of crystal defects in the MgO film adjacent to the interface. After oxygen annealing at 400°C, however, it showed no hysteresis and a low interface trap density of the order of 1011 cm-2eV-1 was achieved with no formation of a low-dielectric layer at the MgO/Si interface. These results indicate that MgO thin films are applicable as gate insulators of FETs. After a PZT film was deposited on the MgO/Si structure, the C-V characteristic of the stacked structure showed a ferroelectric hysteresis curve and a low interface trap density of 5×1011 cm-2eV-1. A maximum memory window width of 1.2 V was obtained for the PZT thin film on Si substrate with a MgO intermediate layer.

Si 3 N 4 on GaAs by direct electron cyclotron resonance plasma assisted nitridation of Si layer in Si/GaAs structure

Si 3 N 4 has been produced on GaAs with low interface trap densities by electron cyclotron resonance N2–He plasma assisted nitridation of a Si layer deposited on a GaAs (100) substrate. Nitridation at 150 and 400 °C was monitored by x-ray photoelectron spectroscopy (XPS) and produced stoichiometric Si3N4. The nitride layer thickness, as determined from XPS as a function of photoelectron takeoff angle, initially increased rapidly with nitridation time with a transition at a thickness of 12–18 Å to slower growth. Capacitance/voltage and conductance/angular frequency measurements were performed on metal-insulator-semiconductor capacitors fabricated from the nitrided samples. The results demonstrated interface trap densities with a minimum of 3.0×1011 eV−1 cm−2 when nitrided at 150 °C. At 400 °C the nitridation produced a poor quality interface, which resulted either from the higher temperature or from nitridation of all of the Si, leaving the Si3N4 in direct contact with the GaAs.

Rapid thermal postoxidation anneal engineering in thin gate oxides with Al gates

The effects of rapid thermal postoxidation annealing (POA) on the characteristics of thin gate oxides, /spl sim/10 nm, were systematically studied with respect to POA time, temperature and pressure. Two kinds of rapid thermal POA techniques were examined. One (POA1) was carried out by switching oxygen into nitrogen immediately after oxidation, while the other (POA2) was done by cooling down first and subsequently heating again in pure nitrogen. It was experimentally observed that the samples annealed by POA2 have larger charge-to-breakdown, Q/sub BD/, and lower interface trap density, D/sub itm/, than those annealed by POA1. But, the samples annealed by POA2 will result in poor immunity to radiation damage. In addition, it is also found that the samples with high POA temperature and low POA pressure treatments have large improvement in Q/sub BD/, but have serious degradation in the radiation hardness. A reoxidation technique after POA was used to improve the radiation hardness degraded by POA.

Effect Of No On The Electrical Characteristics Of SiO2 Grown On P-Type 4H SiC

ABSTRACTIn this paper the effect of NO nitridation on the electrical characteristics of the oxides grown on p-type 4H SiC has been investigated. The results show that NO nitrided oxide has a lower interfacial trap density and a lower net oxide charge compared to N2 annealed oxides.

Electrical Properties of Fully Epitaxial PZT/MgO/Si Stacked Structures for Nonvolatile Future Memory Devices

AbstractFully epitaxial Pb (Zr,Ti)O3(PZT)/MgO/Si(001) stacked structures, one of the potential components of ferroelectric-gate FETs, have been fabricated and characterized. According to the structural and electrical characterization of MgO/Si structures, epitaxially grown MgO thin films on the Si substrates showed a small leakage current of ∼ 10−8 A/cm2 at the electric field of 1 MV/cm. In the C-V measurements of the as-grown MgO/Si heteroepitaxial interfaces, injection-type hysteresis was observed because of the crystal defects in the MgO film adjacent to the interface. Using oxygen annealing with a temperature of 400 °C, it showed no hysteresis and a lower interface trap density of the order of 1011 cm−2eV−1 could be achieved with no formation of a low dielectric layer at the MgO/Si interface. These results indicate that the epitaxial MgO thin films are applicable as the gate insulators of FETs. After the PZT film was deposited on the MgO/Si structure, the C-V characteristic of the stacked structure showed a ferroelectric hysteresis curve and the low interface trap density of 5 × 1011 cm−2eV−1 A maximum memory window width of 1.2 V could be obtained in the PZT thin film on the Si substrate with a MgO intermediate layer.

Thin-gate oxides prepared by pure water anodization followed by rapid thermal densification

Anodic oxidation at room temperature with pure deionized water as electrolyte and then followed by high-temperature rapid thermal densification was used to prepare high breakdown endurance thin-gate oxides with thicknesses of about 50 /spl Aring/. It was observed that the oxides prepared by anodic oxidation followed by rapid thermal densification (AOD) show better electrical characteristics than those grown by rapid thermal oxidation (RTO) only. The AOD oxides have a very low midgap interface trap density, Ditm, of smaller than 1/spl times/10/sup 10/ eV/sup -1/ cm/sup -2/ and negative effective oxide trapped charge. From the smaller leakage currents observed during staircase ramp voltage time-zero dielectric breakdown (TZDB) and constant field time-dependent dielectric breakdown (TDDB) testings, it is supposed that the uniform interfacial property and the pretrapped negative charges in AOD oxides are responsible for the improved characteristics.

Electrical properties of composite gate oxides formed by rapid thermal processing

In this study, oxide stacks formed by combinations of rapid thermal chemical vapor deposition and rapid thermal oxidation have been investigated as gate dielectrics. This was achieved by performing various types of in situ rapid thermal oxidations both prior to and after oxide deposition to form composite stacked structures. The oxidation ambient and temperature was varied to study the effect on electrical properties such as mobility, leakage current, charge trapping, breakdown and hot carrier degradation. It was found that pre-oxidation prior to depositing an oxide results in a composite structure that greatly reduces the defect density by mismatching pores and weak spots in each film. The mobility behavior of these films was also found to be improved over as-deposited oxides. Post-deposition oxidation in O/sub 2/ and N/sub 2/O was also found to improve the mobility characteristics. Additionally, post-annealing in N/sub 2/O was effective in improving the reliability of deposited oxides. These N/sub 2/O annealed films had low interface trap densities, improved high field mobility, very low charge trapping characteristics and enhanced resistance to hot carrier induced interface state generation. These improvements are attributed to 1) the presence of nitrogen at the interface and 2) to the reduction of nitrogen and hydrogen concentrations in the bulk of the oxide. The role of atomic oxygen during the post-anneal in N/sub 2/O is discussed along with differences in annealing ambients.

Electron beam deposited lead-lanthanum-zirconate-titanate thin films for silicon based device applications

A simple single-source electron-beam evaporation technique has been used for the deposition of lead-lanthanum-zirconate-titanate (PLZT) thin films for silicon-based device applications. An optimized annealing condition has been established for the formation of crystalline perovskite phases. The effect of the bottom electrodes and the barrier layer on the growth of the films has been studied. Films with good dielectric and optical properties have been obtained under opt- imized conditions. Electrical properties of the films have been evaluated using metal–insulator–semiconductor and metal–insulator–metal structures. A moderately low interface trap density and very low leakage current density demonstrate the potential of the deposited films for device applications.

Properties of SiGe oxides grown in a microwave oxygen plasma

Thin oxide on strained Si1−xGex surface has been grown using a nonelectron cyclotron resonance mode microwave plasma at low temperatures (150–200 °C). An optimized post-oxidation and post-metal annealing cycle has resulted in very low fixed oxide charge density (1.78×1010/cm2) and moderately low interface trap density (2.9×1011/cm2 eV). A controlled in situ hydrogen-plasma treatment to Si1−xGex has been found to be useful in improving the electrical properties of the oxide. The high electron injection phenomena of metal oxide semiconductor capacitors has been used for charge trapping studies of sites normally present in the SiGe oxides. From the position and the extent of current ledge observed as a function of ramped gate voltage, the capture cross section and the total number of traps have been determined.

Metal-insulator-semiconductor structures of InSb/SiO 2 with very lowinterface trap density

MIS structures fabricated using InSb and silicon dioxide with an interface trap density as low as 4 ×1010 cm-2eV-1 have been achieved. This is about one order of magnitude less than any other reported figure for the InSb MIS system. Both capacitance/voltage and conductance techniques have been employed to study the interface properties of InSb/SiO2. A slow state density of < 1010 cm-2 was observed and the dielectric breakdown field of the oxide was greater than 4 mVcm-1.

Plasma-grown oxides on silicon with extremely low interface state densities

Plasma-grown oxides on silicon with midgap interface state densities less than 10 10 cm −2 eV −1 have been obtained using low process temperatures (<120°C). Slow and fast interface state densities were measured over a wide frequency range by two different techniques: the quasistatic (CV) and the conductance ( G p /w ) methods. Careful attention to system apparatus design, cleanliness and operation are thought to be the main factors responsible for the low interface trap densities.

Characteristics of polyimide film deposited by ionized cluster beam

Ionized cluster beam deposition (ICBD) has been employed to fabricate high-purity polyimide (PI) films. Pyromellitic dianhydride and oxydianiline were deposited using dual ionized cluster beam (ICB) sources. X-ray photo-electron spectroscopy shows that the chemical properties of the surface are very sensitive to the ICBD conditions such as cluster ion acceleration voltage and ionization voltage. At optimum ICBD conditions, the PI films have maximum imidization, and negligible impurities (∼ 1% isoimide). A metal-insulator-semiconductor device has been fabricated using PI as an insulator to investigate the interfacial properties. From C− V characteristics, the PI film deposited with ICB is found to have a fairly low interface trap density. The conduction mechanism in ion implanted PI film is described in terms of the conducting grain model. The main factor determining the conductivity in PI is found to be closely related to the deposited damage energy induced by ion irradiation.

Effect of reactive-ion bombardment on the properties of silicon nitride and oxynitride films deposited by ion-beam sputtering

Silicon nitride and oxynitride films of very low hydrogen content have been deposited on silicon at low temperatures (150–200 °C) using ion-beam sputtering. A dual-ion-beam sputtering technique, making simultaneous use of an energetic argon-ion beam to sputter silicon nitride from a target and a low-energy oxygen or nitrogen ion beam to react with the sputtered films on the substrate, has been employed to control the composition of the films. A precise control of film composition independent of deposition rate has been achieved through the control of oxygen/nitrogen ion-beam parameters and gas flow ratios. The films have been characterized by the measurement and study of refractive index, chemical etch rate, infrared absorption, and x-ray photoelectron spectra. A direct correlation between film properties with oxygen content has been obtained for silicon oxynitride films. The electrical properties have been studied by the measurement of the characteristics of metal-insulator-semiconductor capacitors fabricated using the deposited films. In situ ion-beam oxidation of silicon prior to the oxynitride deposition has resulted in a film with a low insulator charge number density (3.5×1011 cm−2) and interface trap density (4×1011 cm−2 eV−1), which is suitable for device applications.

Electrical properties of thermal oxide grown on n-type 6H-silicon carbide

Measurement of current conduction in the metal/thermal oxide/n-type 6H-silicon carbide is reported. The thermal oxides were grown on nitrogen-doped n-type 6H-silicon carbide at 1275 °C in a dry oxygen ambient. Analysis indicates a Fowler–Nordheim type current conduction mechanism with a barrier height of 2.7 eV between silicon carbide and oxide. Using this value an electron affinity of 3.7–3.8 eV was determined for the Si face of 6H-silicon carbide. The breakdown field strength for the oxides grown on n-type 6H-silicon carbide was 10 MV/cm which is comparable to the breakdown field strength of thermal oxides grown on silicon. Capacitance-voltage measurements indicated that the interface between n-type silicon carbide and the thermally grown oxide has a low (5×1010 cm−2 eV−1) interface trap density (Dit). The effective charge density in the oxide was estimated to be 1×1011 cm−2. These measurements indicate that the quality of oxides thermally grown on 6H-silicon carbide is comparable to those grown on silicon.

GaAs metal insulator semiconductor capacitors and high transconductance metal insulator semiconductor field effect transistors

We have fabricated 3 μm gate length self-aligned, depletion mode GaAs metal insulator semiconductor field effect transistors exhibiting transconductances, typically in the vicinity of 160 mS/mm. This achievement is attributed to the use of Si3N4 as the gate dielectric with a few monolayers of a Si/Ge interface layer between the GaAs channel layer and the insulator. The Si3N4/Si/Ge insulator structure is grown in situ using a plasma-enhanced chemical vapor deposition system which is connected by an ultrahigh vacuum transfer tube to an adjacent III-V molecular beam epitaxy system. Nearly ideal capacitance-voltage curves (compared to previous publications) suggest the existence of a high quality insulator/semiconductor interface. The lowest interface trap density that has been measured, as determined from the magnitude of the conductance peak is ∼2×1011 eV−1 cm−2.

Conductance study of silicon nitride/InP capacitors with an In2S3 interface control layer

Conductance measurements of the SiNx/n-InP interface with an In2S3 interface control layer show the presence of electron traps, with capture cross section of 5.6×10−18 cm2, near the conduction band that increase in density towards the band edge. Carrier accumulation at the interface and response from bulk traps lead to single time constant conductance peaks. The loss is dominated by interface states in accumulation and by bulk states in depletion and weak inversion. The study indicates that low interface trap densities are achieved in the InP band gap for Ec−E≳0.24 eV in agreement with capacitance-voltage results.

Increase in effective carrier lifetime of silicon at low carrier injection levels

The increase in the effective carrier lifetime of oxidized p-type silicon at low carrier injection levels is studied from the viewpoint of silicon surface effects. The effective carrier lifetime is measured by a microwave photoconductive decay method. A gold/oxide/silicon structure is used to examine the dependence of effective carrier lifetime on injected carrier concentration. The effective carrier lifetime is measured at various voltages applied between the gold electrode and the silicon substrate in order to change the silicon surface conditions, i.e. accumulation, depletion or inversion. Increase in the effective carrier lifetime at low carrier injection levels is observed only when the inversion layer is induced at the silicon surface. The increase in effective carrier lifetime may be due to slow recombination of excess minority carriers stored in the inversion layer at the SiO2/Si interface with a low interface trap density and/or slow diffusion of the excess minority carriers into the bulk of the silicon.