Low Interface Trap Density Research Articles

Comparative Study of 4H-SiC DMOSFETs with N<sub>2</sub>O Thermal Oxide and Deposit Oxide with Post Oxidation Anneal

Two kinds of gate oxides, direct thermal oxidation in a nitrous oxide ambient at 1250°C(TGO) and a PECVD oxide followed by a post deposition oxidation in nitrous at 1150°C (DGO) were studied. DGO showed a lower interface trap density and was able to provide a higher current as being implemented in MOSFETs through the improved channel mobility. However the 6.45 MV/cm average breakdown field of DGO is lower than the 10.1 MV/cm breakdown field of TGO. The lower breakdown field, more leaky behavior and the existence of multiple breakdown mechanisms suggest that DGO needs further improvements before it can be used in real applications.

Formation of amorphous Yb2O3/crystalline ZrTiO4 gate stack and its application in n-MOSFET with sub-nm EOT

Dielectric stack composed of orthorhombic ZrTiO4 and amorphous Yb2O3 interfacial layer was employed as the gate dielectric for Si n-MOSFET. The gate stack with EOT of 0.79nm demonstrates a desirable dielectric quality in terms of a low interface trap density (Dit) of 2.4×1011cm−2eV−1 and a small fixed oxide charge density of 2.8×1011cm−2. The promising transistor characteristics are evidenced by the excellent subthreshold swing of 66mV/dec and good electron mobility of 192cm2/Vs at 1MV/cm. The former is primarily due to the low Dit value while the latter is ascribed to the small amount of fixed oxide charge and the existence of an Yb2O3 interfacial layer; both factors are beneficial to suppress the carrier remote scattering mechanism. From the analysis of positive bias temperature instability with the stress field of 11MV/cm for 1000s at 85°C, 12-mV shift in threshold voltage and negligible degradation in subthreshold swing and transconductance prove the satisfactory reliability performance. These prominent electrical characteristics show that the crystalline-based gate stack is eligible for aggressively scaled CMOS devices.

The role of solution-processed high-κ gate dielectrics in electrical performance of oxide thin-film transistors

We developed a simple and environmentally friendly spin-coating method for high-κ dielectrics (AlOx, ZrOx, YOx and TiOx). These materials were used as gate dielectrics for solution-processed nanocrystalline In2O3 or amorphous InZnO TFTs with a maximum processing temperature of 300 °C. The role of high-κ dielectrics in device performance was systematically studied. Among the high-κ dielectrics, the AlOx-based devices showed the best performance with mobilities of 21.7 cm2 V−1 s−1 in an In2O3 TFT and 11.6 cm2 V−1 s−1 in an InZnO TFT with the on/off current ratio exceeding 106. Furthermore, the devices exhibited ultra-low operating voltages (<3 V) and negligible hysteresis. A comprehensive study suggests that the high performance of the AlOx-based devices could be attributed to the smooth dielectric/semiconductor interface and the low interface trap density besides its good insulating properties. Therefore, the solution-processed AlOx can be used as a promising high-κ dielectric for low cost, low voltage, high-performance oxide electronic devices.

Exploration of yttria films as gate dielectrics in sub-50 nm carbon nanotube field-effect transistors.

Thin yttria films were investigated for use as gate dielectrics in carbon nanotube field-effect transistors (CNTFETs) with the gate length scaled down to sub-50 nm size. The yttria film provided an omega-shaped gate dielectric with a low interface trap density, a low average sub-threshold swing of 74 mV per decade for both long and short CNTFETs, and a small drain-induced barrier lowering. It was also shown that the performance of CNTFETs increases with decreasing temperature, with an excellent sub-threshold swing of 22 mV per decade at liquid nitrogen temperatures. A method was developed to retrieve the interface trap density in CNTFETs and a low interface trap density of 5.2 × 10(6) cm(-1) was achieved, indicating the high electric quality of the yttria films.

Double gate dielectric stacks with Gd2O3 layer for application in NVSM devices

This work presents the feasibility study of application of gadolinium trioxide (Gd2O3) layers in double-gate dielectrics stacks for non-volatile semiconductor memories (NVSM). In the course of this work metal–insulator–semiconductors (MIS) structures with SiO2/Gd2O3 stacks have been fabricated and characterised by means of current–voltage (I–V) and split-CV techniques. Moreover, memory characteristics were investigated and compared to MIS structures with stacks based on atomic layer deposited (ALD) hafnium dioxide (HfO2) and aluminum trioxide (Al2O3) layers. Presented results have shown low leakage current density of fabricated SiO2/Gd2O3 of the order of 10−6A/cm2 at 5MV/cm of equivalent electric field intensity, low interface trap density (Nit) ∼2×1011cm−2 and moderate mobility of MISFETs with studied stacks in the range of 140–380cm2V−1s−1. Moreover, the decrease of retention time extrapolated at ten years of the order of 12% was determined which is significantly lower in comparison to MIS stacks with ALD high-k dielectric layers. In the case of MISFET’s threshold voltage (Ut) relatively broad memory window has been obtained around 1.67V which makes the investigated double-gate dielectric stack as the potential candidate for low voltage memory applications.

Germanium oxynitride gate interlayer dielectric formed on Ge(100) using decoupled plasma nitridation

Germanium Oxynitride (GeON) gate interlayer (IL) dielectric formed using decoupled plasma nitridation (DPN) technique is compared with GeO2 and thermally nitrided GeON ILs for Ge gate stack applications using n-channel capacitors and transistors. Lower nitrogen concentration and roughness at the GeON/Ge interface lead to lower midgap interface trap density (Dit) and 1.5× higher electron mobility for the DPN versus thermally nitrided GeON IL. DPN GeON IL also exhibits enhanced thermal stability till 575 °C at the expense of a small degradation in Dit versus GeO2 IL, making it a more viable gate IL dielectric on Ge channels.

Role of high-frequency power in C4F8 dual-frequency capacitively coupled plasmas treating high-k HfO2 films

Plasma treatment of HfO2 films by octafluorocyclobutane (C4F8) 60 MHz(HF)/2 MHz(LF) dual-frequency capacitively coupled plasmas (DF-CCPs) was investigated. It is found that the fluorine atoms were incorporated into the HfO2 films by C4F8 DF-CCP treatment, but the C : F films were formed on the surface of the HfO2/Si gate stacks. The results also show that both the plasma treatment and the process of post-deposition annealing play major roles in stabilizing the tetragonal structure, leading to a large band gap and good electrical properties. The formation of t-HfO2 is related to oxygen vacancy generation and Si diffusion into the HfO2 films. The capacitance–voltage measurement showed that the smallest ΔVfb and the lowest interface trap density were obtained at the HF power of 120 W and the LF power of 30 W. Therefore, the C4F8 DF-CCP is a suitable method to improve the electrical characteristics of HfO2/Si gate stacks.

High performance p-type organic thin film transistors with an intrinsically photopatternable, ultrathin polymer dielectric layer

A high-performing bottom-gate top-contact pentacene-based oTFT technology with an ultrathin (25–48nm) and electrically dense photopatternable polymeric gate dielectric layer is reported. The photosensitive polymer poly((±)endo,exo-bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) is patterned directly by UV-exposure (λ=254nm) at a dose typical for conventionally used negative photoresists without the need for any additional photoinitiator. The polymer itself undergoes a photo-Fries rearrangement reaction under UV illumination, which is accompanied by a selective cross-linking of the macromolecules, leading to a change in solubility in organic solvents. This crosslinking reaction and the negative photoresist behavior are investigated by means of sol–gel analysis. The resulting transistors show a field-effect mobility up to 0.8cm2V−1s−1 at an operation voltage as low as −4.5V. The ultra-low subthreshold swing in the order of 0.1Vdec−1 as well as the completely hysteresis-free transistor characteristics are indicating a very low interface trap density. It can be shown that the device performance is completely stable upon UV-irradiation and development according to a very robust chemical rearrangement. The excellent interface properties, the high stability and the small thickness make the PNDPE gate dielectric a promising candidate for fast organic electronic circuits.

Low-Interface-Trap-Density and High-Breakdown-Electric-Field SiN Films on GaN Formed by Plasma Pretreatment Using Microwave-Excited Plasma-Enhanced Chemical Vapor Deposition

We investigated the SiN/gallium nitride (GaN) interface properties formed by the microwave-excited plasma-enhanced chemical vapor deposition (PECVD) with SiH4/N2/H2 gases. The interface and insulating properties of SiN films on GaN formed by the microwave-excited PECVD strongly depend on SiH4 flow rate. Although the interface trap density is lower than $10^{11}$ cm $^{\mathrm {-2}}$ eV $^{\mathrm {-1}}$ at the relatively high SiH4 flow rate of 1 sccm, the breakdown electric field is very low ( $\sim 1$ MV/cm). Using the SiH4 plasma pretreatment before the stoichiometric SiN deposition, both low interface trap density and high breakdown voltage greater than 2 MV/cm are obtained. In this case, the clearly ordered Ga bonding near the SiN/GaN interface is estimated by an electron energy loss spectroscopy. The formation of SiN film on GaN using the microwave-excited PECVD is a very useful technique for the high-quality interface properties.

New method for determining flat-band voltage in high mobility semiconductors

The method that is commonly used for determining the flat-band voltage (VFB) and the flat-band capacitance (CFB) of metal oxide semiconductor (MOS) capacitors depends on many parameters and can only be used in the case of low interface trap density (Dit) when the capacitance–voltage measurements are carried out at high frequencies. This paper demonstrates a new and simple method for determining VFB and CFB. The method is based on the point of inflection in the capacitance–voltage curve. This method does not require the knowledge of material or experimental parameters and can be used on high Dit and high border trap density MOS structures at all frequencies.

Improved electrical properties of Ge metal-oxide-semiconductor devices with HfO2 gate dielectrics using an ultrathin GeSnOx film as the surface passivation layer

A surface passivation method for improving the interface quality of HfO2 gate dielectric on Ge substrate by using an ultrathin GeSnOx layer is reported. The GeSnOx layer is fabricated using a unique method. A GeSn layer is formed by sputtering Sn on Ge substrate and then removing the top Sn layer with diluted HCl solution. The ultrathin GeSn layer translates into the GeSnOx layer during thermal oxidation in an oxygen atmosphere. It is found that the electrical properties can be improved significantly for Ge/HfO2 devices with the introduction of a GeSnOx layer, including low midgap interface trap density and extremely low leakage current density of the gate stack.

High quality Ge surface passivation layer formed by thermal oxidation of Y/Ge structure

The YGeOx enjoys a low interface trap density of 2.1i?1011cm-2eV-1.Low leakage current of 3.1i?10-10A/cm2 at the effective electric field of 1MV/cm.13mV flatband voltage shift for BTI test under 10MV/cm for 8000s at 85?C. YGeOx formed by thermal oxidation of Y/Ge structure was confirmed by X-ray photoelectron spectroscopy (XPS) and its eligibility as the passivation layer for Ge MOS devices was explored in this work. Because of the thermal oxidation nature of the process that effectively suppresses dielectric structural defects and incorporates sufficient Y atoms at the interface to well passivate the dangling bonds on Ge surface; the YGeOx enjoys a small amount of oxide traps and a low interface trap density (Dit) of 2.1i?1011cm-2eV-1. In addition, the thermally grown YGeOx demonstrates a relatively high dielectric constant of 10.8 as compared to GeO2, tiny frequency dispersion in capacitance-voltage (C-V) characteristics, low leakage current of 3.1i?10-10A/cm2 at the effective electric field of 1MV/cm, 13mV flatband voltage (Vfb) shift for bias temperature instability measurement under the stress condition of 10MV/cm for 8000s at 85?C, these promising device characteristics attest to the eligibility of the YGeOx as the passivation layer for high-performance Ge MOS technology.

Electrical characterization of gadolinium oxide deposited by high pressure sputtering with in situ plasma oxidation

In this work, we characterized gadolinium oxide films deposited on silicon by high pressure sputtering with a two-step process: first, we sputtered metallic gadolinium in an argon atmosphere and then, we performed an in situ plasma oxidation of the metallic layer previously deposited. By means of high resolution transmission electron microscopy, we can detect the oxidation degree of the metallic film. Under optimized deposition conditions, fully oxidized Gd2O3 films are obtained. In addition, the capacitance and conductance as a function of gate voltage of Pt gated metal–insulator–semiconductor capacitors confirm stable dielectric behavior of the fully oxidized films. The devices show low gate leakage currents (∼10−5 A/cm2 at 1 V for 2.2 nm of equivalent oxide thickness), low interface trap density and an almost negligible hysteresis and frequency dispersion.

Passivation mechanism of thermal atomic layer-deposited Al2O3 films on silicon at different annealing temperatures

Thermal atomic layer-deposited (ALD) aluminum oxide (Al2O3) acquires high negative fixed charge density (Qf) and sufficiently low interface trap density after annealing, which enables excellent surface passivation for crystalline silicon. Qf can be controlled by varying the annealing temperatures. In this study, the effect of the annealing temperature of thermal ALD Al2O3 films on p-type Czochralski silicon wafers was investigated. Corona charging measurements revealed that the Qf obtained at 300°C did not significantly affect passivation. The interface-trapping density markedly increased at high annealing temperature (>600°C) and degraded the surface passivation even at a high Qf. Negatively charged or neutral vacancies were found in the samples annealed at 300°C, 500°C, and 750°C using positron annihilation techniques. The Al defect density in the bulk film and the vacancy density near the SiOx/Si interface region decreased with increased temperature. Measurement results of Qf proved that the Al vacancy of the bulk film may not be related to Qf. The defect density in the SiOx region affected the chemical passivation, but other factors may dominantly influence chemical passivation at 750°C.

Interface engineering and chemistry of Hf-based high-k dielectrics on III–V substrates

Recently, III–V materials have been extensively studied as potential candidates for post-Si complementary metal-oxide-semiconductor (CMOS) channel materials. The main obstacle to implement III–V compound semiconductors for CMOS applications is the lack of high quality and thermodynamically stable insulators with low interface trap densities. Due to their excellent thermal stability and relatively high dielectric constants, Hf-based high-k gate dielectrics have been recently highlighted as the most promising high-k dielectrics for III–V-based devices. This paper provides an overview of interface engineering and chemistry of Hf-based high-k dielectrics on III–V substrates. We begin with a survey of methods developed for generating Hf-based high-k gate dielectrics. To address the impact of these hafnium based materials, their interfaces with GaAs as well as a variety of semiconductors are discussed. After that, the integration issues are highlighted, including the development of high-k deposition without Fermi level pinning, surface passivation and interface state, and integration of novel device structure with Si technology. Finally, we conclude this review with the perspectives and outlook on the future developments in this area. This review explores the possible influences of research breakthroughs of Hf-based gate dielectrics on the current and future applications for nano-MOSFET devices.

Confinement and integration of magnetic impurities in silicon

Integration of magnetic impurities into semiconductor materials is an essential ingredient for the development of spintronic devices such as dilute magnetic semiconductors. While successful growth of ferromagnetic semiconductors was reported for III-V and II-VI compounds, efforts to build devices with silicon technology were hampered by segregation and clustering of magnetic impurities such as manganese (Mn). Here, we report on a surface-based integration of Mn atoms into a silicon host. Control of Mn diffusion and low-temperature silicon epitaxy lead to confined Mn δ-layers with low interface trap densities, potentially opening the door for a new class of spintronic devices in silicon.

Enhanced Inversion Mobility on 4H-SiC $(\hbox{11}\overline{\hbox{2}} \hbox{0})$ Using Phosphorus and Nitrogen Interface Passivation

Low interface trap density and high channel mobility on nonpolar faces of 4H-SiC, such as the (11[2]0) a-face, are of fundamental importance in the understanding of SiC MOS devices. It is also critical for high-voltage trench power MOSFET development. We report new results on the passivation of the SiO2/a-face 4H-SiC interface using phosphorus, yielding field effect mobility of ~125 cm2/V · s. We also revisit the conventional NO passivation, for which a mobility of ~85 cm2/V · s was achieved on the a-face. These results not only establish new levels of mobility in SiC MOSFETS but also lead to further insights into factors currently limiting SiC inversion layer mobility.

High-Mobility Stable 4H-SiC MOSFETs Using a Thin PSG Interfacial Passivation Layer

Phosphorous from P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> is more effective than nitrogen for passivating the 4H-SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface. The peak value of the field-effect mobility for 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) after phosphorus passivation is approximately 80 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s. However, P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> converts the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer to phosphosilicate glass (PSG)-a polar material that introduces voltage instabilities which negate the benefits of lower interface trap density and higher mobility. We report a significant improvement in voltage stability with mobilities as high as 72 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s for MOSFETs fabricated with a thin PSG gate layer ( ~ 10 nm) capped with a deposited oxide.

Effect of NH&lt;sub&gt;3&lt;/sub&gt; Post-Oxidation Annealing on Flatness of SiO&lt;sub&gt;2&lt;/sub&gt;/SiC Interface

We investigated the effects of the post-oxidation annealing (POA) atmosphere on the electrical properties and interfacial roughness of SiO2 deposited on a 4H-SiC (0001) face and SiC. POA in ammonia (NH3) gave MOS capacitors with a lower interface trap density and n-channel MOSFETs with higher field-effect mobility than POA in nitrous oxide (N2O) or nitrogen (N2). In contrast, POA in N2O gave a lower interface trap density than POA in N2, but it gave the lowest field-effect mobility of all the samples. Cross-sectional TEM observations revealed that N2O POA gave a higher interfacial roughness than NH3 POA. We thus considered that N2O POA degraded the inversion-layer mobility due to increased roughness scattering.

Heteroepitaxy of La2O3 and La2–xYxO3 on GaAs (111)A by Atomic Layer Deposition: Achieving Low Interface Trap Density

GaAs metal-oxide-semiconductor devices historically suffer from Fermi-level pinning, which is mainly due to the high trap density of states at the oxide/GaAs interface. In this work, we present a new way of passivating the interface trap states by growing an epitaxial layer of high-k dielectric oxide, La(2-x)Y(x)O(3), on GaAs(111)A. High-quality epitaxial La(2-x)Y(x)O(3) thin films are achieved by an ex situ atomic layer deposition (ALD) process, and GaAs MOS capacitors made from this epitaxial structure show very good interface quality with small frequency dispersion and low interface trap densities (D(it)). In particular, the La(2)O(3)/GaAs interface, which has a lattice mismatch of only 0.04%, shows very low D(it) in the GaAs bandgap, below 3 × 10(11) cm(-2) eV(-1) near the conduction band edge. The La(2)O(3)/GaAs capacitors also show the lowest frequency dispersion of any dielectric on GaAs. This is the first achievement of such low trap densities for oxides on GaAs.