Low Interface Trap Density Research Articles

Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5−90 nm), the SiO2 thickness (3−4 nm), and as well the SiGe-shell thickness (2−15 nm) has been demonstrated, enabling a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5x10^11 cm^-2·eV^-1 and fixed charge densities of 1-5x10^11 cm^-2, suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1-xGex shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.

Reliability study of high-κ La2O3/HfO2 and HfO2/La2O3 stacking layers on n-In0.53Ga0.47As metal–oxide–semiconductor capacitor

This study investigates the time-dependent dielectric breakdown (TDDB) characteristics of La2O3/HfO2 and HfO2/La2O3 stacking layers on an n-In0.53Ga0.47As metal–oxide–semiconductor capacitor. Both designs improved the reliability compared with a single layer of HfO2. The TDDB followed the thermochemical E model. The current transportation mechanism changed from thermionic emission to Frenkel–Poole emission because of the traps creation under voltage stress. Both designs resulted in similar lifespans and voltage accelerating factors. However, the La2O3/HfO2 design had a longer lifespan because of the lower interface trap density and insertion of the HfO2 diffusion barrier layer between La2O3 and n-In0.53Ga0.47As. The oxide stacks exhibited excellent reliability and achieved a lifespan of 28.4 years.

Plasma Enhanced Atomic Layer Deposition Passivated HfO<sub>2</sub>/AlN/In<sub>0.53</sub>Ga<sub>0.47</sub>As MOSCAPs With Sub-Nanometer Equivalent Oxide Thickness and Low Interface Trap Density

The impact of in situ plasma-enhanced atomic layer deposition passivation on the electrical properties of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As metal-oxide-semiconductor capacitors (MOSCAPs) has been studied. Excellent interface quality of high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /III-V is achieved by aluminum nitride (AlN) interfacial passivation layer, including strong inversion behaviors and unpinned Fermi level. The band alignment of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /AlN/In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As structure with the valence band offsets of 2.81 ± 0.1 eV and the conduction band offsets of 1.9 ± 0.1 eV was obtained. Better interface and optimized high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectric qualities are achieved using post remote-plasma treatment with either N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> or NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gases. Sub-nanometer equivalent oxide thickness HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /AlN/In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As MOSCAPs with low interface trap density and low leakage current density have been characterized.

Density-Functional Theory Molecular Dynamics Simulations and Experimental Characterization of a-Al₂O₃/SiGe Interfaces.

Density-functional theory molecular dynamics simulations were employed to investigate direct interfaces between a-Al2O3 and Si0.50Ge0.50 with Si- and Ge-terminations. The simulated stacks revealed mixed interfacial bonding. While Si-O and Ge-O bonds are unlikely to be problematic, bonding between Al and Si or Ge could result in metallic bond formation; however, the internal bonds of a-Al2O3 are sufficiently strong to allow just weak Al bonding to the SiGe surface thereby preventing formation of metallic-like states but leave dangling bonds. The oxide/SiGe band gaps were unpinned and close to the SiGe bulk band gap. The interfaces had SiGe dangling bonds, but they were sufficiently filled that they did not produce midgap states. Capacitance-voltage (C-V) spectroscopy and angle-resolved X-ray photoelectron spectroscopy experimentally confirmed formation of interfaces with low interface trap density via direct bonding between a-Al2O3 and SiGe.

Low‐thermal budget flash light annealing for Al2O3 surface passivation

This value is achieved due to a very low interface trap density of below 1010 eV–1 cm–2 and a fixed charge density of (2–3) × 1012 cm–2. In contrast, plasma ALD‐grown Al2O3 layers only reach carrier lifetimes of about 1 ms. This is mainly caused by a more than 10 times higher density of interface traps, and thus, inferior chemical passivation. The strong influence of the deposition parameters is explained by the limitation of hydrogen transport in Al2O3 during low‐thermal budget annealing. (© 2015 WILEY‐VCH Verlag GmbH &amp;Co. KGaA, Weinheim)

Effect of high voltage stress on the DC performance of the Al2O3/AlN GaN metal–insulator–semiconductor high-electron mobility transistor for power applications

We demonstrate an Al2O3/AlN/AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistor (MIS-HEMT) device with stable electrical properties under high-voltage stress, by using an Al2O3/AlN stack layer as the gate dielectric layer. Excellent quality AlN/Al2O3 GaN interface was obtained by using plasma-enhanced ALD (PE-ALD), resulting in a very low interface trap density (Dit) of ∼1.8 × 1011 eV−1 cm−2, obtained by using the conductance method. The device exhibits a small threshold voltage hysteresis of ∼200 mV and a lower gate–source leakage current. No obvious changes in the drain–source current and ON-resistance were observed for the device that was subject to the drain–source voltage stress of 100 V for 15 h.

High-mobility and low-operating voltage organic thin film transistor with epoxy based siloxane binder as the gate dielectric

This paper reports the fabrication of pentacene-based organic thin-film transistors using a dielectric material, Dynasylan ®SIVO110. The devices exhibit excellent performance characterized by a low threshold voltage of −1.4 V (operating voltage: 0 to −4 V) together with a mobility of 1.9 cm2 V−1s−1. These results are promising because it uses only a single layer of dielectric without performing any intermediate treatment. The reason is attributed to the high charge storage capacity of the dielectric (κ ∼ 20.02), a low interfacial trap density (2.56 × 1011cm−2), and favorable pentacene film morphology consisting of large and interconnected grains having an average size of 234 nm.

Improvement of interfacial and electrical properties of Al2O3/ n-Ga0.47In0.53As for III-V impact ionization MOSFETs

In this work, Metal - Oxide - Semiconductor Capacitors (MOSCaps) based on Al2O3/ n-Ga0.47In0.53As interface have been studied. In order to have high MOSFETs performance, it is necessary to improve the semiconductor - oxide interface quality. It is observed that the (NH4)2S passivation shows lower interface trap density in the order of 6×1011cm-2.eV-1. Also, it is observed that O2 plasma densification after a passivation in a NH4OH solution improves the electrical behaviour of the charge control. Low interface trap density in the order of 1×1012cm-2.eV-1 was obtained for different treatments presented in this work.

Interfacial and electrical properties of radio frequency sputtered ultra-thin TiO2 film for gate oxide applications

The electrical responses of ultra-thin TiO2 films in the form of Al/TiO2/Si capacitors prepared by rf sputtering, have been studied in a wide frequency range as a function of post deposition annealing temperature. Thickness, interfacial and surface roughnesses of the heterostructures were extracted by fitting the specular X-ray reflectivity data. The TiO2 film annealed at 800 °C exhibited negligible hysteresis in the capacitance–voltage curve with the lowest interface trap density of 3.18 × 1011 cm−2 eV−1 extracted using Hill-Coleman method. Minimum equivalent oxide thickness (EOT) of 1.67 nm was obtained for the film annealed at annealed at 800 °C with leakage current density of 7.4 × 10−4 A/cm2 at −2 V. Space charge limited current (SCLC) conduction mechanism has been found to be dominant for the film annealed at 400 °C; however for the film annealed at 800 °C, it was found that at lower voltage (<2.5 V) the conduction mechanism is governed by SCLC with a transition to Fowler–Nordheim tunnelling at voltages higher than 2.5 V.

Reducing the interface trap density in Al2O3/InP stacks by low-temperature thermal process

By applying low-temperature processes below 300 °C, high-performance Al/Al2O3/InP metal–insulator–semiconductor capacitors with low interface trap density and small capacitance frequency dispersion at the accumulation regime are demonstrated. A minimum interface trap density of 1.2 × 1011 cm−2 eV−1 near the midgap is obtained. The impacts of thermal treatment on interface traps, thermal stability, and interfacial bonding configurations are studied and discussed. It is found that interface trap density could be significantly reduced by removing phosphorus and its oxides at low temperature (250–300 °C), while further increasing the thermal treatment temperature is harmful to interface quality.

Surface passivation of crystalline silicon by sputtered AlOx/AlNx stacks toward low-cost high-efficiency silicon solar cells

Recently, excellent surface passivation has been achieved for both p- and n-type silicon solar cells using AlOx/SiNx:H stacks deposited by atomic layer deposition and plasma-enhanced chemical vapor deposition. However, alternative materials and deposition methods could provide practical options for large-scale manufacturing of commercial solar cells. In this study we demonstrate that AlOx/AlNx stacks fabricated by reactive radio-frequency magnetron sputtering can provide fairly good surface passivation (Smax of ∼30 cm/s) regardless of AlOx thickness, which is found to be due to the high negative fixed charge density (Qeff of −2.8 × 1012 cm−2) and moderately low interface trap density (Dit of 2.0 × 1011 eV−1·cm−2). The stacks also show fairly good antireflection performance in the visible and near-infrared spectral region. The demonstrated surface passivation and antireflection performance of in situ reactively sputtered AlOx/AlNx stacks make them a promising candidate for a surface-passivating antireflection coating on silicon solar cells.

Low-voltage operation of ZrO2-gated n-type thin-film transistors based on a channel formed by hybrid phases of SnO and SnO2.

With SnO typically regarded as a p-type oxide semiconductor, an oxide semiconductor formed by hybrid phases of mainly SnO and a small amount of SnO2 with an average [O]/[Sn] ratio of 1.1 was investigated as a channel material for n-type thin-film transistors (TFTs). Furthermore, an appropriate number of oxygen vacancies were introduced into the oxide during annealing at 400 °C in ambient N2, making both SnO and SnO2 favorable for current conduction. By using high-κ ZrO2 with a capacitance equivalent thickness of 13.5 nm as the gate dielectric, the TFTs processed at 400 °C demonstrated a steep subthreshold swing (SS) of 0.21 V/dec, and this can be ascribed to the large gate capacitance along with a low interface trap density (Dit) value of 5.16 × 10(11) cm(-2) eV(-1). In addition, the TFTs exhibit a relatively high electron mobility of 7.84 cm(2)/V·s, high ON/OFF current ratios of up to 2.5 × 10(5), and a low gate leakage current at a low operation voltage of 3 V. The TFTs also prove its high reliability performance by showing negligible degradation of SS and threshold voltage (VT) against high field stress (-10 MV/cm). When 3% oxygen annealing is combined with a thinner channel thickness, TFTs with even higher ION/IOFF ratios exceeding 10(7) can also be obtained. With these promising characteristics, the overall performance of the TFTs displays competitive advantages compared with other n-type TFTs formed on binary or even some multicomponent oxide semiconductors and paves a promising and economic avenue to implement an n-type oxide semiconductor without doping for production-worthy TFT technology. Most importantly, when combined with the typical SnO-based p-type oxide semiconductor, it would usher in a new era in achieving high-performance complementary metal oxide semiconductor circuits by using the same SnO-based oxide semiconductor.

Suppression of dark current in GeOx-passivated germanium metal-semiconductor-metal photodetector by plasma post-oxidation.

We propose GeOx passivation by plasma post-oxidation for dark-current suppression in a germanium (Ge) photodetector (PD). A GeOx/Ge interface exhibits a significantly lower interface trap density than SiO2/Ge and Al2O3/Ge interfaces. GeOx passivation on a Ni/Ge Schottky diode decreases the dark current under -1 V bias by more than one order of magnitude compared with Al2O3 passivation, which is attributed to the reduction in the surface leakage current. We also evaluated the Ge surface potential to study its effect on the surface leakage current. It was found that the surface leakage is suppressed when the accumulation condition of the Ge surface is enhanced as a result of fixed charges in the passivation layer. Thus, we have revealed the importance of a low interface trap density at the Ge surface and a suitable number of fixed charges in the passivation layer for achieving a low dark current in Ge metal-semiconductor-metal (MSM) PDs. Finally, we have examined the effect of GeOx passivation on a normal-incidence Ge MSM PD. We observed a significant decrease in the dark current in the GeOx-passivated samples, and a dark current of 97 nA under -1 V bias was achieved under the optimal GeOx passivation conditions.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step.

We report a first-of-its-kind, unique approach for generating a self-aligned, gate-stacking heterostructure of Ge quantum dot (QD)/SiO2/SiGe shell on Si in a single fabrication step. The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials. The high-quality interface properties of our “designer” heterostructure are evidenced by the low interface trap density of as low as 2–4 × 1011 cm−2 eV−1 and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions. We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.

Self-aligned inversion-channel n-InGaAs, p-GaSb, and p-Ge MOSFETs with a common high κ gate dielectric using a CMOS compatible process

Y2O3, as a common high κ gate dielectric, has been directly deposited on (In)GaAs, GaSb, and Ge using electron beam evaporation in ultra-high vacuum. These semiconductors have distinctly different chemical bonding and surface electronic characteristics. No interfacial passivation layer was employed. High-quality Y2O3/semiconductor interfaces have been achieved, resulting in low interfacial trap densities and high-temperature thermal stability, essential for the CMOS compatible process. Self-aligned inversion channel n-InGaAs, p-GaSb, and p-Ge MOSFETs have been fabricated with excellent device performances.

(Invited) Preparation of GaSb Surface for Low Interfacial Trap Density MOS Capacitors

High mobility III-V compound semiconductors have been extensively investigated recently for future complementary metal-oxide-semiconductor (CMOS) applications. GaSb, which has high electron and hole mobilities as well as a narrow bandgap is an attractive material for future high-speed and low-power integrated circuits. Due to the easy formation of native oxides, i.e. SbOx, GaOx, and elemental Sb clusters on GaSb surface, Fermi-level pinning and high interfacial trap density (Dit) has been a major obstacle to high quality MOS devices. In this talk, we will present both in-situ and ex-situ techniques to prepare GaSb surface and realize metal-oxide-semiconductor capacitors (MOSCAPs) with low interfacial trap density. The i n-situ approach is conducted in a system equipped with a high vacuum sample transfer tube that connects a molecular beam epitaxy (MBE) tool and an atomic layer deposition (ALD) chamber. A native oxide-free surface can thus be preserved for high-κ dielectrics deposition. HfO2/Al2O3/GaSb MOSCAPs fabricated on Sb-stabilized surface exhibit clear inversion behavior at low frequency and good modulation of the Fermi level across the whole GaSb band gap. Modulation of the inversion capacitance at 100 kHz reaches 30 %, suggesting low Dit as well as low bulk trap density at the interface. The Dit extracted by the conductance method is about 7.6×1011 cm-2eV-1 near the valence band. As to the ex-situ process, air-exposed GaSb samples are treated by hydrogen plasma at room temperature prior to ALD dielectrics. Under optimized plasma treatment conditions, similar C-V characteristics and gate leakage current of HfO2/Al2O3/GaSb MOSCAPs to those of the in-situ ones are observed. Modulation of the inversion capacitance at 100 kHz even reaches 36 % and the Dit near the valence band is as low as 6.0×1011 cm-2eV-1. Structural and chemical analyses of the dielectric/semiconductor interface by high-resolution transmission electron microscopy (HRTEM) and x-ray photoelectron spectroscopy (XPS) show that the in-situ MOSCAPs have a native oxide-free interface, while hydrogen plasma treatment results in the formation of GaOx, which may serve to passivate defects and dangling bonds at the GaSb surface

Improved Structural and Electric Characterstics of Al/ALD-HfO2/Ge MOS Capacitor by Germanium Dioxide and Germanium Oxynitride as Interfacial Layer

In this work HfO2 thin films has been deposited on Ge substrate by ALD with thickness of 9.77 nm. Thickness evaluation of film was done by Spectroscopic Ellipsometer (SE) and Filmetrics Reflectometer whereas chemical compositions and the states of the elements of the films were investigated by X-ray Photoelectron Spectroscopy (XPS). High-frequency Capacitance-Voltage (C-V), Conductance-Voltage (G-V) techniques and Current-Voltage (I-V) measurement were used to obtain the electrical properties of the high-k MOS capacitor. Different Ge surface cleaning methods preceding high-k ALD have been used for reducing oxide traps. Rapid Thermal Oxidation (RTO) and Rapid Thermal Nitridation (RTN) have been used to form the gate interlayer (IL) of GeO2 and GeON for the gate stack of P-MOS capacitor. By assimilating a thin GeON interlayer, excellent MOS capacitors with very small capacitance–voltage hysteresis and low gate leakage have been demonstrated. Physical and Electrical characterization investigates the quality of the oxynitride interlayer and low interface trap density (Dit ≈ 0.63×1012eV-1cm-2) in case of GeON/Ge which is improved as compared to the GeO2/Ge interface (Dit ≈ 2.53×1013 eV-1cm-2). Further electrical characterizations of HfO2 gate dielectric MOS capacitors deposited by the ALD using RTO & RTN as IL were investigated for the measurement of EOT and Qeff. The calculated EOT and Qeff values for GeON/Ge are 3.23 nm and 16.92×1012 cm-2 respectively which is better in comparison with GeO2 and as deposited samples.

Cellulose-Derivative-Based Gate Dielectric for High-Performance Organic Complementary Inverters.

been realized using organic thin-fi lm transistors (OTFTs) as the essential element. In the majority of these applications OTFTs are integrated either in the form of arrays or as digital logic. The fundamental building block of digital logic is the inverter, a circuit that inverts an input signal. Much work has been devoted in the last fi ve years to design unipolar inverters using p-typeonly OTFTs. [ 18‐23 ] Unfortunately, unipolar logic based on single gate OTFTs always suffers from high power consumption and low noise margin coupled with high noise margin variability and therefore impedes the fabrication of complex circuits having hundreds or more logic gates. [ 19,22,23 ] In this context, it stands

(Invited) Preparation of GaSb Surface for Low Interfacial Trap Density MOS Capacitors

The effects of i n-situ and ex-situ surface treatments on the electrical properties of GaSb metal-oxide-semiconductor capacitors (MOSCAPs) are compared and investigated. The in-situ approach can provide a native oxide-free GaSb surface subsequent high-κ dielectric deposition. HfO2/Al2O3/p-GaSb MOSCAPs fabricated on an Sb-stabilized surface exhibit clear inversion at low frequency and good modulation of the Fermi level across the whole GaSb band gap. The interfacial trap density (Dit) extracted by the conductance method is about 7.6×1011 cm-2eV-1 near the valence band. As to the ex-situ process, the air-exposed GaSb samples are treated by hydrogen plasma at room temperature prior to dielectric deposition. The capacitance-voltage (C-V) characteristics and gate leakage currents are comparable to those of the MOSCAPs prepared by in-situ method. Dit near the valence as low as 6.0×1011 cm-2eV-1is obtained, indicating the feasibility of using GaSb p-channel MOSFETs for future complementary MOS integrated circuits.