Low Interface Trap Density Research Articles

Role of Annealing Conditions on Surface Passivation Properties of ALD Al2O3 Films

The surface passivation performance of Al2O3 films attracted attention in the field of solar cells and semiconductor devices and depends on the conditions of the applied post-deposition annealing step. The effect of annealing temperature and different annealing atmospheres on the surface passivation quality of atomic layer deposited Al2O3 films was investigated on n-type float-zone Si wafers. Photoconductance decay measurements were carried out to characterize recombination velocities and carrier lifetimes. The chemical and field-effect passivation mechanism, i.e. the interface trap density and the fixed charge density, respectively, were studied by capacitance-voltage experiments. Low surface recombination velocities of Seff,max ∼1cm/s corresponding to a carrier lifetime of 9.0ms were achieved for samples annealed in O2 atmosphere whereas annealing in H2 and N2 led to slightly higher Seff,max-values ∼2cm/s. The annealing temperature was found to affect both the fixed charge density and the interface trap density whereas in contrast the annealing atmosphere affected only the interface trap density, i.e. the chemical passivation. According to the expectations the highest surface passivation quality is based on a high fixed charge density and a low interface trap density.

Influence of Atomic Layer Deposition Temperatures on TiO2/n-Si MOS Capacitor

This paper reports on the influence of deposition temperature on the structure, composition, and electrical properties of TiO2 thin films deposited on n-type silicon (100) by plasma-assisted atomic layer deposition (PA-ALD). TiO2 layers ∼20 nm thick, deposited at temperatures ranging from 100 to 300°C, were investigated. Samples deposited at 200°C and 250°C had the most uniform coverage as determined by atomic force microscopy. The average carbon concentration throughout the oxide layer and at the TiO2/Si interface was lowest at 200°C. Metal oxide semiconductor capacitors (MOSCAPs) were fabricated, and profiled by capacitance-voltage techniques. The sample prepared at 200°C had negligible hysteresis (from a capacitance-voltage plot) and the lowest interface trap density (as extracted using the conductance method). Current-voltage measurements were carried out with top-to-bottom structures. At −2 V gate bias voltage, the smallest leakage current was 1.22 × 10−5 A/cm2 for the 100°C deposited sample.

The combination self-cleaning effect of trimethylaluminium and tetrakis (dimethyl-amino) hafnium pretreatments on GaAs

The self-cleaning effect of trimethylaluminium (TMA) and tetrakis (dimethyl-amino) hafnium (TDMAH) pretreatments on GaAs substrates was investigated deeply. The chemical states were carefully characterized by the X-ray photoelectron spectroscopy, which demonstrates that the pretreatment before ALD of dielectric films can suppress the formation of native oxides on GaAs substrates effectively. It is found that the combination of TMA and TDMAH pretreatments has better self-cleaning effect than single TMA pretreatment based on a ligand-exchange reaction mechanism between TMA/TDMAH and the native oxide. The transmission electron microscopy images also show a thinnest interlayer thickness of ∼0.2nm for the TMA+TDMAH pretreated sample. TMA+TDMAH pretreated samples exhibit significantly improved interfacial and electrical properties such as the highest accumulation capacitance, the least stretch-out of capacitance–voltage curves, and the lowest interface trap density. These results indicate that the surface pretreatment by using the combination of TMA and TDMAH pulses may be a promising approach for the realization of high quality GaAs-based transistor devices.

Properties of thermally oxidized and nitrided Zr-oxynitride thin film on 4H–SiC in diluted N2O ambient

A systematic investigation on the structural, chemical, and electrical properties of thermally oxidized and nitrided sputtered Zr thin film in various N2O ambient (10–100%) at 500 °C for 15 min to form Zr-oxynitride on 4H–SiC substrate has been carried out. The chemical composition, depth profile analysis, and energy band alignment have been evaluated by X-ray photoelectron spectrometer. Zr-oxynitride layer and its interfacial layer comprised of compounds related to Zr–O, Zr–N, Zr–O–N, Si–N, and/or C–N were identified. A model related to the oxidation and nitridation mechanism has been suggested. Supportive results related to the model were obtained by energy filtered transmission electron microscopy, X-ray diffraction, and Raman analyses. A proposed crystal structure was employed to elucidate the surface roughness and topographies of the samples, which were characterized by atomic force microscopy. The electrical results revealed that 10% N2O sample has possessed the highest breakdown field and reliability. This was owing to the confinement of nitrogen-related compounds of Zr–O–N and/or Zr–N at or near interfacial layer region, smaller grain with finer structure on the surface, the lowest interface trap density, total interface trap density, and effective oxide charge, and highest barrier height between conduction band edge of oxide and semiconductor.

Effects of SF6 plasma treatment on electrical characteristics of TaN-Al2O3-InP metal-oxide-semiconductor field-effect transistor

The effects of SF6 plasma treatment of Al2O3 on InP substrate have been investigated in this paper. Electrical characteristics including drive current, effective channel mobility, transconductance, subthreshold swings, etc., have been compared for devices with SF6 plasma treatment at different power (P = 30 or 50 W) for different time (t = 3, 5, or 7 min). With 5 min SF6 plasma treatment at power = 30 W, the maximum drive current is increased by 20% to 60.2 μA/μm and effective channel mobility is increased by 36.7% to 1099 cm2/V s for devices on InP substrate with 7 nm Al2O3 (EOT ∼ 3.4 nm and W/L = 600 μm/10 μm). It is believed S and F atoms are incorporated into Al2O3 bulk and Al2O3/InP interface, so that better oxide quality and a lower interface trap density are achieved by SF6 plasma treatment at optimal power with optimal time duration.

MOS Devices With High-κ (ZrO$_2$) $_x$(La $_2$O$_3$) $_{1-x}$ Alloy as Gate Dielectric Formed by Depositing ZrO $_2$/La$_2$O $_3$/ZrO$_2$ Laminate and Annealing

An amorphous (ZrO2)x(La2O3)1-x alloy formed by depositing a ZrO2/La2O3/ZrO2 laminate and a subsequent annealing was employed as the gate dielectric for metal-oxide-semiconductor (MOS) devices. The (ZrO2)x(La2O3)1-x alloy is found to have a high permittivity κ of 26.2 with negligible amount of bulk traps, both of which are very desirable for advanced gate dielectrics. By integrating the (ZrO2)x(La 2O3)1-x alloy with an SiON interfacial layer as the gate stack, it displays good frequency dispersion in capacitance-voltage (C -V) characteristics and low interfacial trap density of 1.52 × 1011 cm-2 eV-1. In addition, the current conduction mechanism of the gate stack is observed to be Fowler-Nordheim tunneling and the leakage current of 3.6 × 10-6 A/cm2 at the gate voltage of -1 V for equivalent oxide thickness of 1.1 nm can be achieved, which is superior to other high-κ dielectrics. Furthermore, satisfactory reliability is verified by bias temperature instability measurement. Most importantly, this gate stack not only exhibits a promising perspective for advanced CMOS technology but introduces a more reliable process to form an alloy-based high-κ gate dielectric.

Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks

The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (100) Ge down to 3×1011eV−1cm−2 are demonstrated. The formation of the high-k LaxGeyOz layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.

Integration of Amorphous $\hbox{Yb}_{2}\hbox{O}_{3}$ and Crystalline $\hbox{ZrTiO}_{4}$ as Gate Stack for Aggressively Scaled MOS Devices

Because of a higher permittivity than Al2O3, a large conduction band offset and high thermal stability, a thin amorphous Yb2O3 layer was integrated with a ZrTiO4 film as the gate stack for advanced Si MOS devices. With 800 °C annealing, the ZrTiO4 film can be crystallized in orthorhombic phase with permittivity of 45.9 and a gate stack with equivalent oxide thickness of 0.86 nm can be achieved. This crystalline ZrTiO4/Yb2O3 gate stack demonstrates negligible frequency dispersion in capacitance, low interface trap density of 1.86 × 1011 cm-2 eV-1, leakage current of 6.7 × 10-6 A/cm2 at gate bias of Hatband voltage (VFB) -1 V, and high extrapolated 10-year lifetime operating voltage of -2.9 V. These promising electrical characteristics suggest that the crystalline ZrTiO4/Yb2O3 gate stack holds great potential to be applied to aggressively scaled CMOS technology.

Comparison of thermal and atomic-layer-deposited oxides on 4H-SiC after post-oxidation-annealing in nitric oxide

The electrical properties of thermally grown and atomic-layer-deposition (ALD) oxides, followed by nitridation treatment, on 4H-SiC substrate were compared. The nitridation treatment was performed with post oxidation annealing in NO atmosphere (NO POA). The best electrical characteristics of the thermally grown and ALD oxides were observed at 120 and 180 min NO POA, respectively. The NO POA treated ALD oxide showed extremely low interface trap density (Dit), less than 1011 eV−1 cm−1. A metal-oxide-semiconductor field-effect-transistor with the ALD oxide showed high field effect mobility, especially in the high electric field region. The reasons for these superior results were also discussed.

Cumulative effects of electrode and dielectric surface modifications on pentacene-based transistors

Surface modifications of the dielectric and the metal of pentacene-based field effect transistors using self-assembled monolayer (SAM) were studied. First, a low interfacial trap density and pentacene 2D-growth were favored by the nonpolar and low surface energy of octadecyltrichlorosilane-based SAM. This treatment leaded to increased mobility up to 0.4 cm2 V−1 s−1 and no observable hysteresis on transfer curves. Second, reduced hole injection barrier and contact resistance were achieved by fluorinated thiols deposited on gold contacts resulting in an increased mobility up to 0.6 cm2 V−1 s−1. Finally, a high mobility of 2.6 cm2 V−1 s−1 was achieved by cumulative effects of both treatments.

Synthesis, interface (Au/M2Pc2/p-Si), electrochemical and electrocatalytic properties of novel ball-type phthalocyanines

The phthalodinitrile derivative (3) was prepared by the reaction of 4,4'-(octahydro-4,7-methano-5H-inden-5-ylidene)bisphenol (1) and 4-nitrophthalonitrile (2) with dry DMF as the solvent in the presence of the base K(2)CO(3) by the method of nucleophilic substitution of an activated nitro group in an aromatic ring. The template reaction of 3 with the corresponding metal salts gave the novel bi-nuclear ball-type metallophthalocyanines, MPcs {M = Co (4), Cu (5), Zn (6)}. Newly synthesized compounds were characterized by elemental analysis, UV-vis, FT-IR (ATR), MALDI-TOF mass and (1)H-NMR spectroscopy techniques. The electronic spectra exhibit an intense π→π* transition of characteristic Q and B bands of the Pc core. The dielectric properties and interface between the spin coated films of 4-6 and a p-type silicon substrate have been studied by fabricating metal-insulator-semiconductor capacitors. The results indicated that the frequency dependence of the dielectric permittivity, ε'(ω), exhibits non-Debye type relaxation for all the temperatures investigated. The ac conductivity results indicated that the conduction mechanism can be explained by a hopping model at low temperatures (<430 K) and a free band conduction mechanism at high temperatures (≥430 K). The density of interface state calculations on these novel compounds showed that the combination of Au/4/p-Si is a promising structure with a high dielectric constant and a low interface trap density suitable for metal-oxide-semiconductor devices. The electrochemical properties of the Pc complexes were examined by cyclic voltammetry, differential voltammetry and controlled potential coulometry on platinum in non-aqueous media. The complexes showed ring-based and/or metal-based mixed-valence behaviours as a result of the remarkable interaction between the two Pc rings and/or metal centres. The mixed-valence splitting values for the complexes suggested that the mixed valence species are considerably stable. The Vulcan XC-72(VC)/Nafion(Nf)/4 modified glassy carbon electrode showed much a higher catalytic performance towards oxygen reduction than those of VC/Nf/5 and VC/Nf/6 modified ones.

Stability of La2O3 and GeO2 passivated Ge surfaces during ALD of ZrO2 high-k dielectric

La2O3 grown by atomic layer deposition (ALD) and thermally grown GeO2 are used to establish effective electrical surface passivations on n-type (100)-Ge substrates for high-k ZrO2 dielectrics, grown by ALD at 250°C substrate temperature. The electrical characterization of MOS capacitors indicates an impact of the Ge-surface passivation on the interfacial trap density and the frequency dependent capacitance in the inversion regime. Lower interface trap densities can be obtained for GeO2 based passivation even though a chemical decomposition of the oxidation states occur during the ALD of ZrO2. As a consequence the formation of a ZrGeOx compound inside the ZrO2 matrix and a decline of the interfacial GeO2 are observed. The La2O3 passivation provides a stable amorphous lanthanum germanate phase at the Ge interface but also traces of Zr germanate are indicated by X-ray-Photoelectron-Spectroscopy and Transmission-Electron-Microscopy.

Phosphorous passivation of the SiO 2/4H–SiC interface

We describe experimental and theoretical studies to determine the effects of phosphorous as a passivating agent for the SiO 2/4H–SiC interface. Annealing in a P 2O 5 ambient converts the SiO 2 layer to PSG (phosphosilicate glass) which is known to be a polar material. Higher mobility (approximately twice the value of 30–40 cm 2/V s obtained using nitrogen introduced with an anneal in nitric oxide) and lower threshold voltage are compatible with a lower interface defect density. Trap density, current–voltage and bias-temperature stress (BTS) measurements for MOS capacitors are also discussed. The BTS measurements point to the possibility of an unstable MOSFET threshold voltage caused by PSG polarization charge at the O–S interface. Theoretical considerations suggest that threefold carbon atoms at the interface can be passivated by phosphorous which leads to a lower interface trap density and a higher effective mobility for electrons in the channel. The roles of phosphorous in the passivation of correlated carbon dangling bonds, for SiC counter-doping, for interface band-tail state suppression, for Na-like impurity band formation and for substrate trap passivation are also discussed briefly.

Effect of sputtering time on physical and electrical properties of ZrOx thin film on Si

PurposeThe purpose of this paper is to report the effect of sputtering time on the electrical and physical properties of ZrOx. ZrOx (measured thickness is ranging from 20.5 to 51.3 nm) thin films as gate oxide materials are formed by metal deposition at different sputtering time and thermal oxidation techniques.Design/methodology/approachZirconium is deposited on silicon substrate at three different sputtering time; 30‐, 60‐ and 120‐s continued with an oxidation process conducted at 500°C for 15 min to form ZrOx thin films. High‐resolution X‐ray diffraction (HR‐XRD), Fourier transform infrared (FTIR) spectroscopy and electrical characterizations were used to examine the properties of the thin film.FindingsA broad ZrOx peak lies in between 26° and 31° from HR‐XRD is presumed as the effect of small thickness of ZrOx and or the ZrOx is still partially crystalline. FTIR spectroscopy results suggested that besides ZrOx, SiOx interfacial layer (IL) has also formed in all of the investigated samples. As the sputtering time increases, hysteresis between the forward and reverse bias of capacitance‐voltage curve has reduced. The lowest leakage current density and the highest oxide breakdown voltage have been demonstrated by 60‐s sputtered sample. These may be attributed to a lower effective oxide charge and interface trap density. The extracted dielectric constant (κ) of these oxides is ranging from 9.4 to 18, in which the κ value increases with the increase in sputtering time.Originality/valueZrOx thin film which was fabricated by sputtering method at different sputtering time and thermal oxidation techniques showed distinctive electrical results. SiOx IL formed in the samples.

Low interfacial trap density and sub-nm equivalent oxide thickness in In0.53Ga0.47As (001) metal-oxide-semiconductor devices using molecular beam deposited HfO2/Al2O3 as gate dielectrics

We investigated the passivation of In0.53Ga0.47As (001) surface by molecular beam epitaxy techniques. After growth of strained In0.53Ga0.47As on InP (001) substrate, HfO2/Al2O3 high-κ oxide stacks have been deposited in-situ after surface reconstruction engineering. Excellent capacitance-voltage characteristics have been demonstrated along with low gate leakage currents. The interfacial density of states (Dit) of the Al2O3/In0.53Ga0.47As interface have been revealed by conductance measurement, indicating a downward Dit profile from the energy close to the valence band (medium 1012 cm−2eV−1) towards that close to the conduction band (1011 cm−2eV−1). The low Dit’s are in good agreement with the high Fermi-level movement efficiency of greater than 80%. Moreover, excellent scalability of the HfO2 has been demonstrated as evidenced by the good dependence of capacitance oxide thickness on the HfO2 thickness (dielectric constant of HfO2 ∼20) and the remained low Dit’s due to the thin Al2O3 passivation layer. The sample with HfO2 (3.4 nm)/Al2O3 (1.2 nm) as the gate dielectrics has exhibited an equivalent oxide thickness of ∼0.93 nm.

GaSb Inversion-Mode PMOSFETs With Atomic-Layer-Deposited $\hbox{Al}_{2}\hbox{O}_{3}$ as Gate Dielectric

GaSb inversion-mode PMOSFETs with atomic-layer-deposited (ALD) Al2O3 as gate dielectric are demonstrated. A 0.75- μm-gate-length device has a maximum drain current of 70 mA/mm, a transconductance of 26 mS/mm, and a hole inversion mobility of 200 cm2/V ·s. The off-state performance is improved by reducing the ALD growth temperature from 300°C to 200°C. The measured interface trap distribution shows a low interface trap density of 2 × 1012/cm2·eV near the valence band edge. However, it increases to 1 - 4 ×1013/cm2 ·eV near the conduction band edge, leading to a drain current on-off ratio of 265 and a subthreshold swing of ~ 600 mV/decade. GaSb, similar to Ge, is a promising channel material for PMOSFETs due to its high bulk hole mobility, high density of states at the valence band edge, and, most importantly, its unique interface trap distribution and trap neutral level alignment.

Crystalline ZrO2-gated Ge metal-oxide-semiconductor capacitors fabricated on Si substrate with Y2O3 as passivation layer

By adopting an amorphous Y2O3 passivation layer, which provides a wide band gap and well passivates Ge surface without the presence of GeOx, a high-permittivity (κ) crystalline ZrO2/Y2O3 stack was explored as the gate dielectric for Ge metal-oxide-semiconductor (MOS) devices on Si substrate. The crystalline ZrO2 is a Ge stabilized tetragonal/cubic dielectric with the κ value of 36.1 and was formed by depositing a ZrO2/Ge/ZrO2 laminate and a subsequent 500 °C annealing. The high-κ crystalline ZrO2/Y2O3 gate stack shows promising electrical characteristics in terms of low interface trap density of 5.8×1011 cm−2 eV−1, negligible hysteresis, and leakage current of 5.6×10−4 A/cm2 at gate bias of flatband voltage (VFB) 1 V for equivalent oxide thickness of 1.13 nm. This gate stack not only demonstrates the eligibility for advanced Ge MOS devices but introduces a more reliable process to form a high-κ crystalline gate dielectric.

Influence of post-deposition annealing in oxygen ambient on metal–organic decomposed CeO2 film spin coated on 4H-SiC

Post-deposition annealing (PDA) was performed in oxygen ambient at different temperatures (600, 800, 1,000 and 1,150 °C) onto metal–organic decomposition (MOD) prepared CeO2 film spin coated on n-type 4H-SiC substrate. Effects of PDA onto the physical and electrical characteristics of MOD-derived CeO2 were investigated. Four orientations [(111), (200), (220), and (311)] of CeO2 peaks were revealed by X-ray diffraction analysis in all of the samples with a preferred orientation in (200) direction. However, α-Ce2O3 and cerium silicate (Ce2Si2O7) interfacial layers emerged at 1,150 °C. As annealing temperature increased, grain size of films was increased but microstrains were decreased. Electrical results indicated that negative effective oxide charge and slow trap density were decreased as temperature increased. The lowest interface trap density was perceived by sample annealed at 1,000 °C. However, the highest electric field was obtained by sample annealed at 1,150 °C. Reasons that contributed to this observation were discussed.

Effect of surface preparation and interfacial layer on the quality of SiO2/GaN interfaces

In this work, SiO2/GaN MOS structures have been fabricated using Electron Cyclotron Resonance Plasma Enhanced Chemical Vapor Deposition (ECR-PECVD) for deposition of silicon dioxide (SiO2) at low temperature (300 °C) on N-type, NID and P-type GaN epitaxial layers. Surface preparation involving chemical, UV-Ozone oxidation and oxygen plasma oxidation have been investigated by XPS analysis of the GaN surfaces prior to SiO2 deposition. The association of UV ozone and plasma oxidation allows a complete removal of carbon contamination and has a huge beneficial effect on the quality of the SiO2/GaN interface. Electrical C-V characterizations put into evidence the improved quality of the SiO2/GaN interface with a low interface trap density of 1010 cm−2 eV−1. The advantage of this soft interface treatment is thus specially observed for the N-type samples without annealing step, whereas improvements are still needed in the case of NID and P-type samples.

Al-doped HfO2/In0.53Ga0.47As metal-oxide-semiconductor capacitors

Hafnium oxide gate dielectrics doped with a one to two percent of aluminum are grown on In0.53Ga0.47As channels by codeposition of trimethylaluminum (TMA) and hafnium tertbutoxide (HTB). It is shown that the addition of TMA during growth allows for smooth, amorphous films that can be scaled to ∼5 nm physical thickness. Metal-oxide-semiconductor capacitors (MOSCAPs) with this dielectric have an equivalent oxide thickness of 1 nm, show an unpinned, efficient Fermi level movement and lower interface trap densities than MOSCAPs with HfO2 dielectrics grown by sequential TMA/HTB deposition.