Low Interface Trap Density Research Articles

Al 2 O 3 / GeO x / Ge gate stacks with low interface trap density fabricated by electron cyclotron resonance plasma postoxidation

An electron cyclotron resonance (ECR) plasma postoxidation method has been employed for forming Al2O3/GeOx/Ge metal-oxide-semiconductor (MOS) structures. X-ray photoelectron spectroscopy and transmission electron microscope characterizations have revealed that a GeOx layer is formed beneath the Al2O3 capping layer by exposing the Al2O3/Ge structures to ECR oxygen plasma. The interface trap density (Dit) of Au/Al2O3/GeOx/Ge MOS capacitors is found to be significantly suppressed down to lower than 1011 cm−2 eV−1. Especially, a plasma postoxidation time of as short as 10 s is sufficient to reduce Dit with maintaining the equivalent oxide thickness (EOT). As a result, the minimum Dit values and EOT of 5×1010 cm−2 eV−1 and 1.67 nm, and 6×1010 cm−2 eV−1 and 1.83 nm have been realized for Al2O3/GeOx/Ge MOS structures with p- and n-type substrates, respectively.

Publisher’s Note: “Attainment of low interfacial trap density absent of a large midgap peak in In0.2Ga0.8As by Ga2O3 (Gd2O3) passivation” [Appl. Phys. Lett. 98, 062108 (2011)

Publisher’s Note: “Attainment of low interfacial trap density absent of a large midgap peak in In0.2Ga0.8As by Ga2O3 (Gd2O3) passivation” [Appl. Phys. Lett. 98, 062108 (2011)

Attainment of low interfacial trap density absent of a large midgap peak in In0.2Ga0.8As by Ga2O3(Gd2O3) passivation

The pronounced high interfacial densities of states (Dit) commonly observed around the midgap energy of dielectric/GaAs interfaces are generally considered the culprit responsible for the poor electrical performance of the corresponding inversion-channel metal-oxide-semiconductor field-effect-transistors. In this work, comprehensive Dit spectra as the function of energy [Dit(E)] inside the In0.2Ga0.8As band gap were constructed by using the quasistatic capacitance-voltage and the temperature-dependent conductance method on n- and p-type ultrahigh vacuum (UHV)-Ga2O3(Gd2O3)/In0.2Ga0.8As and atomic-layer-deposited (ALD)-Al2O3/In0.2Ga0.8As metal-oxide-semiconductor capacitors. Unlike the ALD-Al2O3/In0.2Ga0.8As interface giving a Dit spectrum with a high midgap Dit peak, the UHV-Ga2O3(Gd2O3)/In0.2Ga0.8As interface shows a Dit spectrum that monotonically decreases from the valence band to the conduction band with no discernible midgap peak.

Pressure Dependence on the Electrical Properties of SiO2 Gate Oxide Formed by Inductive Coupled Plasma Oxidation

ABSTRACTWe investigated the pressure dependence of the inductive coupled plasma (ICP) oxidation on the electrical characteristics of the thin oxide films. Activation energies and electron temperatures with different pressures were estimated. To demonstrate the pressure effect on the plasma oxide quality, simple N type metal-oxide-semiconductor (NMOS) transistors were fabricated and investigated in a few electrical properties. At higher pressure than 200mTorr, plasma oxide has a slightly higher on-current and a lower interfacial trap density. The on-current gain seems to be related to the field mobility increase and the lower defective interface to the electron temperature during oxidation.

Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO2 Interfacial Layers

We have successfully fabricated high hole mobility Ge p-channel metal–oxide–semiconductor field-effect transistors (p-MOSFETs) with GeO2/Ge formed by direct thermal oxidation, which can yield a significantly low interface trap density (Dit). Al2O3 films are employed as capping layers for protecting the GeO2/Ge MOS interfaces during the MOSFET fabrication processes. The source/drain (S/D) regions are formed by boron ion implantation in a self-align way with Al gate metal. The good MOS interface properties are found to be maintained even after the activation annealing at temperatures sufficient for obtaining the excellent junction properties. The fabricated MOSFETs exhibit high source and drain on/off current ratios of 105–104 and a high peak hole mobility of 575 cm2 V-1 s-1 at maximum, both of which are attributable to the excellent GeO2/Ge MOS interface properties. The effects of the substrate impurity concentration and the thickness of GeO2 on the hole mobility are examined. It is found from the results for different substrate impurity concentrations that the universal curve between hole mobility and the effective field Eeff holds for η= 1/3. We also investigate the impact of the oxidation temperature dependence on hole mobility in order to examine the scattering mechanism limiting the mobility of GeO2/Ge interfaces through the modulation of the MOS interfaces by changing oxidation temperature. It is found that the mobility in low-temperature and low-surface carrier density (Ns) regions is well corrected with Dit evaluated from S factors in MOSFETs. In addition, it is revealed from transmission electron microscopy analyses that the interface roughness between GeO2 and Ge is reduced with increasing oxidation temperature. From these experimental results, the higher mobility of GeO2/Ge p-MOSFET at higher oxidation temperatures can be explained by the reduction in the density of Coulomb scattering centers and surface roughness at elevated Ge oxidation temperatures.

Analysis of interface trap density of metal–oxide-semiconductor devices with Pr 2O 3 gate dielectric using conductance method

In this study, the interface trap density of metal–oxide-semiconductor (MOS) devices with Pr 2O 3 gate dielectric deposited on Si is determined by using a conductance method. In order to determine the exact value of the interface trap density, the series resistance is estimated directly from the impedance spectra of the MOS devices. Subsequently, the dispersion characteristics are numerically analyzed on the basis of a statistical model. Lastly, the process-dependent interface trap density of Pr 2O 3 is evaluated. It is concluded that high-pressure annealing and a superior quality interfacial SiO 2 layer are of crucial importance for achieving a sufficiently low interface trap density.

Schottky barrier SOI-MOSFETs with high-k La2O3/ZrO2 gate dielectrics

Schottky barrier SOI-MOSFETs incorporating a La2O3/ZrO2 high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500°C. Excellent drive current properties, low interface trap densities of 1.9×1011eV−1cm−2, a low subthreshold slope of 70-80mV/decade, and an ION/IOFF current ratio greater than 2×106 are obtained.

Effect of Trap Profile on Device Characteristics of Metal–Oxide–Semiconductor Field Effect Transistors with Hafnium-Based Dielectrics

The trap properties and performance of metal–oxide–semiconductor field effect transistors (MOSFETs) with either a HfSiO or HfO2 dielectric were determined using single-pulse Id–Vg and charge pumping measurements. The HfSiO dielectric shows a lower bulk trap density and a lower interface trap density than the HfO2 dielectric. Particularly, the trap depth profile as a function of distance from the Si/SiOx interface, which is obtained using frequency-dependent charge pumping measurements, shows a marked reduction in trap density in the HfSiO dielectric, unlike in the HfO2 dielectric. This significant reduction in trap density close to the Si/SiOx interface can contribute to the improvement in the carrier mobility of MOSFETs with a HfSiO dielectric.

Control of Interface Traps in HfO2 Gate Dielectric on Silicon

The effects of postdeposition annealing (PDA) on the interface between HfO2 high-k dielectric and bulk silicon were studied in detail. The key challenges of successfully adopting the high-k dielectric/Si gate stack into advanced complementary metal–oxide–semiconductor (CMOS) technology are mostly due to interfacial properties. We have proposed a PDA treatment at 600°C for several different durations (5 min to 25 min) in nitrogen or oxygen (95% N2 + 5% O2) ambient with a 5-nm-thick HfO2 film on a silicon substrate. We found that oxidation of the HfO2/Si interface, removal of the deep trap centers, and crystallization of the film take place during the postdeposition annealing (PDA). The optimal PDA conditions for low interface trap density were found to be dependent on the PDA duration. The formation of an amorphous interface layer (IL) at the HfO2/Si interface was observed. The growth was due to oxygen incorporated during thermal annealing that reacts with the Si substrate. The interface traps of the bonding features, defect states, and hysteresis under different PDA conditions were studied using x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), transmission electron microscopy (TEM), and leakage current density–voltage (J–V) and capacitance–voltage (C–V) techniques. The results showed that the HfO2/Si stack with PDA in oxygen showed better physical and electrical performance than with PDA in nitrogen. Therefore, PDA can improve the interface properties of HfO2/Si and the densification of HfO2 thin films.

Solution-processed zinc–tin oxide thin-film transistors with low interfacial trap density and improved performance

Solution-processed amorphous oxide semiconductors are attractive channel materials in thin-film transistors (TFTs) for low-cost electronics. We demonstrate improved performance and uniformity of solution-processed zinc–tin oxide (ZTO) TFTs by optimizing the prebake process for the ZTO precursor film. ZTO prebake process prearranges the dielectric/semiconductor interface and minimizes the performance variation caused by the uneven thermal distribution during annealing process. Prearranging the interface also reduces interfacial trap density and results in improved performance. A mobility of 27.3 cm2/V s, an on/off ratio of ∼107, and a subthreshold swing of 122 mV/decade have been obtained. Significant improvement in operational stability has also been observed.

Improved electrical and interfacial properties of RF-sputtered HfAlO x on n-GaAs with effective Si passivation

In this paper, we present the effects of ultrathin Si interfacial layer on the physical and electrical properties of GaAs MOS capacitors fabricated using RF-sputtered HfAlO x gate dielectric. It is found that HfAlO x /Si/n-GaAs stack exhibits excellent electrical properties with low frequency dispersion (∼4.8%), hysteresis voltage (0.27 V) and interface trap density (1.3 × 10 12 eV −1 cm −2). The current density of 3.7 × 10 −5 A/cm 2 is achieved with an equivalent-oxide-thickness of 1.8 nm at V FB + 1 V for Si-passivated HfAlO x films on n-GaAs. X-ray photoelectron spectroscopy (XPS) analysis shows that the suppression of low-k interfacial layer formation is accomplished with the introduction of ultrathin Si interface control layer (ICL). Thus the introduction of thin layer of Si between HfAlO x dielectrics and GaAs substrate is an effective way to improve the interface quality such as low frequency dispersion, hysteresis voltage and leakage current. Additionally, current conduction mechanism has been studied and the dominant conduction mechanisms are found to be Schottky emission at low to medium electric fields and Poole–Frenkel at high fields and high temperatures under substrate injection. In case of gate injection, the main current conduction at low field is found to be the Schottky emission at high temperatures.

Investigation of Thermal Stability of TiN Film Formed by Atomic Layer Deposition Using Tetrakis(dimethylamino)titanium Precursor for Metal-Gate Metal–Oxide–Semiconductor Field-Effect Transistor

In this paper, we describe the superiority of the titanium nitride (TiN) film formed by atomic layer deposition (ALD) using a tetrakis(dimethylamino)titanium (TDMAT) precursor for metal-gate electrodes of planar metal–oxide–semiconductor field-effect transistors (MOSFETs). It was demonstrated that the resistivity of the ALD TiN was significantly reduced by NH3 post deposition annealing (PDA). The electrical characteristics of the ALD-TiN-gate MOS capacitors and planar MOSFETs were evaluated and compared with those of the physical-vapor-deposited (PVD) TiN. The performance of the ALD-TiN-gate cases was confirmed to be superior to that of the PVD-TiN-gate cases, which was explained by the lower interface trap density (Dit) of the ALD TiN/SiO2 gate stack.

Electrical Properties of Metal–Insulator–Semiconductor Capacitors on Freestanding GaN Substrate

The electrical properties of GaN metal–insulator–semiconductor (MIS) capacitors with as-grown SiO2, annealed SiO2, and SiNx insulators were investigated by capacitance–voltage (C–V), current–voltage (I–V), and time-dependent dielectric breakdown (TDDB) measurements. The MIS capacitor with the SiNx insulator was determined to have a lower interface trap density of 1×1011 cm-2 eV-1 than the MIS capacitors with the as-grown and annealed SiO2 insulators. In addition, the dielectric lifetime of the SiNx insulator was extrapolated to be more than 20 years at an even high voltage at room temperature. These results indicate that the high insulator/GaN interface quality and high reliability required for high-performance power devices can be achieved by the deposition of the SiNx insulator on GaN.

MOS Characteristics of C-Face 4H-SiC

Metal–oxide–semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) fabricated on the carbon face of 4H-SiC were characterized following different postoxidation annealing methods used to passivate the oxide–semiconductor (O–S) interface. Of the various processes studied, sequential postoxidation annealing in NO followed by atomic hydrogen gave the lowest interface trap density (D it). Direct oxidation/passivation in NO yielded somewhat better I–V characteristics, though all passivation ambients produced approximately the same breakdown field strength. n-Channel MOSFETs showed high channel mobility at low field, which is likely caused by the presence of mobile ions at the O–S interface. Comparisons with the silicon face are presented for interface trap density, oxide breakdown field, and channel mobility. These comparisons suggest that the carbon face does not offer significant performance advantages.

Electrical Properties of Pulsed Laser Deposited Y[sub 2]O[sub 3] Gate Oxide on 4H–SiC

Yttrium oxide (Y 2 0 3 ) has been successfully deposited on n-type 4H-SiC substrates using pulsed laser deposition. The effects of postdeposition annealing temperature (400, 500, and 600°C) on the electrical properties of the Y 2 O 3 gate oxide have been studied in comparison with the as-deposited sample. The sample annealed at 600°C possessed the highest dielectric breakdown field of ∼6.5 MV cm -1 at 10- 6 A cm -2 , resulting from the lowest interface trap density and total interface trap density. The Fowler-Nordheim tunneling mechanism has been investigated on all samples and the highest value of barrier height extracted between the semiconductor and oxide conduction band edges was 2.67 eV.

Influence of postdeposition annealing on structural properties and electrical characteristics of thin Tm 2O 3 and Tm 2Ti 2O 7 dielectrics

We describe the structural properties and electrical characteristics of thin thulium oxide (Tm 2O 3) and thulium titanium oxide (Tm 2Ti 2O 7) as gate dielectrics deposited on silicon substrates through reactive sputtering. The structural and morphological features of these films were explored by X-ray diffraction, X-ray photoelectron spectroscopy, secondary ion mass spectrometry, and atomic force microscopy, measurements. It is found that the Tm 2Ti 2O 7 film annealed at 800 °C exhibited a thinner capacitance equivalent thickness of 19.8 Å, a lower interface trap density of 8.37 × 10 11 eV −1 cm −2, and a smaller hysteresis voltage of ∼4 mV than the other conditions. We attribute this behavior to the Ti incorporated into the Tm 2O 3 film improving the interfacial layer and the surface roughness. This film also shows negligible degrees of charge trapping at high electric field stress.

Metal-oxide–semiconductor characteristics of thermally grown nitrided SiO 2 thin film on 4H-SiC in various N 2O ambient

Metal-oxide–semiconductor characteristics of thermally grown nitrided SiO 2 (9–11.5 nm) on n-type 4H-SiC at 1175 °C in various N 2O ambient (1, 10, and 50% N 2O mixed with 99, 90, and 50% of high purity N 2 gas, respectively) have been investigated. The chemical composition of oxide–semiconductor interface has been evaluated by X-ray photoelectron spectroscopy. The interfacial layer consists of either silicon oxynitride, silicon nitride, and/or silicon oxide phases that may be segregated or mixed in a single layer. Depending on the percentage of N 2O being used, the stoichiometry may vary accordingly. The lowest leakage current density is recorded for thin film oxide grown in10% N 2O and it is limited to an applied electric field of not more than 7 MV/cm. This is attributed to the lowest density value of deep oxide trap in this sample if compared with others. The highest dielectric breakdown field has been obtained for thin film oxide grown in 50% N 2O as this sample is having the lowest interface trap density and negative effective oxide charge. The origin of these charges is explained in the text.

Characterization of Y 2O 3 gate dielectric on n-GaAs substrates

Physical and electrical properties of sputtered deposited Y 2O 3 films on NH 4OH treated n-GaAs substrate are investigated. The as-deposited films and interfacial layer formation have been analyzed by using X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS). It is found that directly deposited Y 2O 3 on n-GaAs exhibits excellent electrical properties with low frequency dispersion (<5%), hysteresis voltage (0.24 V), and interface trap density (3 × 10 12 eV −1 cm −2). The results show that the deposition of Y 2O 3 on n-GaAs can be an effective way to improve the interface quality by the suppression on native oxides formation, especially arsenic oxide which causes Fermi level pinning at high- k/GaAs interface. The Al/Y 2O 3/n-GaAs stack with an equivalent oxide thickness (EOT) of 2.1 nm shows a leakage current density of 3.6 × 10 −6 A cm −2 at a V FB of 1 V. While the low-field leakage current conduction mechanism has been found to be dominated by the Schottky emission, Poole–Frenkel emission takes over at high electric fields. The energy band alignment of Y 2O 3 films on n-GaAs substrate is extracted from detailed XPS measurements. The valence and conduction band offsets at Y 2O 3/n-GaAs interfaces are found to be 2.14 and 2.21 eV, respectively.

Solution-processed flexible organic transistors showing very-low subthreshold slope with a bilayer polymeric dielectric on plastic

We demonstrate low-voltage, solution-processed organic transistors on rough plastic substrates with a carrier mobility over 0.2 cm2/V s, a turn-on voltage of near 0 V, and a record low subthreshold slope of ∼80 mV/decade in ambient conditions. These exceptional characteristics are attributed to (1) a device stacking architecture with a conducting polymeric gate and a double layered dielectric composed of low-temperature cross-linked poly(4-vinylphenol), (2) a low interface trap density achieved by modifying the dielectric surface with a phenyl-terminated self-assembled monolayer from 4-phenylbutyltrichlorosilane, and (3) controlled crystallization of a small-molecule organic semiconductor film with favorable charge transport microstructure and a low bulk trap density as deposited by an optimized solution-shearing process. The device performance under different operating voltages was also examined and discussed.

Electrical study of sulfur passivated In 0.53Ga 0.47As MOS capacitor and transistor with ALD Al 2O 3 as gate insulator

In this paper we compare the interface trap distributions D it(E) of sulfur treated Al 2O 3/In 0.53Ga 0.47As interfaces, which underwent MOS capacitor and transistor fabrication processes. Lower interface trap densities were found close to the conduction band edge for both cases. The inversion channel MOSFET achieves high device performance despite the fact that its oxide-semiconductor interface quality is a notch below that of the MOS capacitor with optimized process.