Low-temperature Solid-phase Crystallization Research Articles

Low-temperature crystallization of BeO-assisted polycrystalline germanium layer for monolithic 3D integration

We demonstrated a new method for the low-temperature solid-phase crystallization (SPC) of germanium on beryllium oxide (BeO) films for monolithic 3D (M3D) integration. Using a wurtzite crystal BeO film, known for its high thermal conductivity of 370 W/m-k at 300 K and covalent bonding characteristics, as the underlying layer, we crystallized Ge at a reduced temperature of 410 °C. For the Ge on BeO, the formation of larger grains was consistently promoted at annealing temperatures of 410–500 °C, with a notable 125 % increase in the grain size at 500 °C compared to that at the SiO2 underlayer. The polycrystalline Ge layers crystallized on the BeO retained their tensile strain, as confirmed by the Raman spectra. Furthermore, its optical bandgap of ∼ 1.36 eV and average roughness of 0.847 nm at an annealing temperature of 450 °C make it more suitable for an M3D upper channel layer than Ge on SiO2. A comprehensive experimental analysis confirmed the enhanced crystallinity, stability, and channel properties of poly-Ge layers crystallized on BeO. Hence, this study developed a new method for the low-temperature SPC process and highlighted the potential of BeO as a crystallization-assistance thermal-management material for next-generation 3D integrated technology.

Strain-dependent grain boundary properties of n-type germanium layers

Polycrystalline Ge thin films have attracted considerable attention as potential materials for use in various electronic and optical devices. We recently developed a low-temperature solid-phase crystallization technology for a doped Ge layer and achieved the highest electron mobility in a polycrystalline Ge thin film. In this study, we investigated the effects of strain on the crystalline and electrical properties of n-type polycrystalline Ge layers. By inserting a GeOx interlayer directly under Ge and selecting substrates with different coefficients of thermal expansion, we modulated the strain in the polycrystalline Ge layer, ranging from approximately 0.6% (tensile) to − 0.8% (compressive). Compressive strain enlarged the grain size to 12 µm, but decreased the electron mobility. The temperature dependence of the electron mobility clarified that changes in the potential barrier height of the grain boundary caused this behavior. Furthermore, we revealed that the behavior of the grain boundary barrier height with respect to strain is opposite for the n- and p-types. This result strongly suggests that this phenomenon is due to the piezoelectric effect. These discoveries will provide guidelines for improving the performance of Ge devices and useful physical knowledge of various polycrystalline semiconductor thin films.

(Invited, Digital Presentation) Nondegenerate Hydrogen-Doped Polycrystalline Indium Oxide (InOx:H) Thin Films for High-Mobility Thin Film Transistors

Transparent metal oxide semiconductors (OSs) have been extensively investigated for use as the active channel layer of thin film transistors (TFTs) for next-generation flat-panel displays, nonvolatile memories, image sensors, and pH sensors, to name a few. Among OSs, the amorphous In–Ga–Zn–O (IGZO) has attracted particular attention for TFT applications owing to its high field effect mobility (μFE) of more than 10 cm2V−1s−1, steep subthreshold swing (S.S.), extremely low off-state current, large-area uniformity, and good bias stress stability. Although the μFE of an IGZO TFT is approximately one order of magnitude higher than that of an amorphous Si TFT, further improvement of the μFE of OS TFTs is required to expand their range of applications as an alternative to polycrystalline Si TFT.Single-crystalline In2O3 has a Hall mobility as high as 160 cm2V−1s−1, which makes amorphous (a-) or polycrystalline (poly-) InOx a potential material for enhancing the μFE of OS TFTs. However, undoped InOx thin films is known as a degenerate semiconductor with high background electron density of over 1020 cm-3, which is attributed to the presence of native defects, such as oxygen vacancies, making them unsuitable for a channel material of OS TFTs. In this presentation, nondegenerate hydrogen-doped polycrystalline InOx (poly-InOx:H) thin films were successfully prepared by low-temperature solid phase crystallization (SPC). A degenerate amorphous InOx:H thin film was deposited by sputtering in Ar, O2, and H2 gases, and an amorphous to polycrystalline phase transition (SPC) of the film was achieved after PDA at more than 175 °C. By PDA at 250 °C in air, a nondegenerate poly-InOx:H film could be obtained with a carrier density as low as 2.4 × 1017 cm−3, which is approximately three orders of magnitude lower than that of the initial a-InOx:H film. The TFTs with a 50 nm thick nondegenerate poly-InOx:H channel could be fully depleted by a gate electric field. A maximum μFE of 125.7 cm2V−1s−1 was exhibited by the TFT with the poly-InOx:H channel. The use of a nondegenerate poly-InOx:H film is a promising approach to boost the μFE of OS TFTs.

(Invited) Hydrogenated Polycrystalline In2O3 (In2O3:H) Thin-Film Transistor with High Mobility Exceeding 100 cm2V−1s−1 Via Solid-Phase Crystallization

Oxide semiconductors have been extensively studied as active channel layers of thin-film transistors (TFTs) for electronic applications. However, the field-effect mobility (μ FE) of oxide TFTs is not sufficiently high to compete with that of low-temperature-processed polycrystalline-Si TFTs (50–100 cm2V−1s−1). Here, we propose a simple process to obtain high-performance TFTs, namely hydrogenated polycrystalline In2O3 (In2O3:H) TFTs grown via the low-temperature solid-phase crystallization (SPC) process. In2O3:H TFTs fabricated at 300 °C exhibit superior switching properties with µ FE = 139.2 cm2V−1s−1. The hydrogen introduced during sputter deposition plays an important role in enlarging the grain size and decreasing the subgap defects in SPC-prepared In2O3:H. The proposed method does not require any additional expensive equipment and/or change in the conventional oxide TFT fabrication process. We believe these SPC-grown In2O3:H TFTs have a great potential for use in future electronic applications.

Influence of Grain Boundary Scattering on the Field-Effect Mobility of Solid-Phase Crystallized Hydrogenated Polycrystalline In2O3 (In2O3:H).

Hydrogenated polycrystalline In2O3 (In2O3:H) thin-film transistors (TFTs) fabricated via the low-temperature solid-phase crystallization (SPC) process with a field-effect mobility (μFE) exceeding 100 cm2 V−1 s−1 are promising candidates for future electronics applications. In this study, we investigated the effects of the SPC temperature of Ar + O2 + H2-sputtered In2O3:H films on the electron transport properties of In2O3:H TFTs. The In2O3:H TFT with an SPC temperature of 300 °C exhibited the best performance, having the largest µFE of 139.2 cm2 V−1 s−1. In contrast, the µFE was slightly degraded with increasing SPC temperature (400 °C and higher). Extended X-ray absorption fine structure analysis revealed that the medium-range ordering in the In2O3:H network was further improved by annealing up to 600 °C, while a large amount of H2O was desorbed from the In2O3:H films at SPC temperatures above 400 °C, resulting in the creation of defects at grain boundaries. The threshold temperature of H2O desorption corresponded well with the carrier transport properties; the µFE of the TFTs started to deteriorate at SPC temperatures of 400 °C and higher. Thus, it was suggested that the hydrogen remaining in the film after SPC plays an important role in the passivation of electron traps, especially for grain boundaries, resulting in an enhancement of the µFE of In2O3:H TFTs.

Experimental Activation Energy for Solid Phase Crystallization of Amorphous Silicon Thin Films at Elevated Temperatures Using Vertical-Cavity Surface-Emitting Laser-Based Infrared Heating

Vertical cavity surface-emitting lasers (VCSELs) were applied to the rapid heating of amorphous Si (a-Si) thin films using high-power infrared illumination at a wavelength of 980 nm, allowing for a high heating rate of up to 200 °C s−1, temperature control of less than 0.1 °C and temporal resolution of 0.1 s. The refined temperature control enabled us to accurately investigate the rapidly evolving period of crystallization in a-Si at a fast speed. The crystallinity and surface morphology were probed using Raman spectroscopy, UV–visible spectroscopy, and atomic force microscopy. The temperature-dependent crystallinity was quantified by fitting the annealing duration time with a sigmoidal curve. Based on the crystallization times in association with the Arrhenius relation, the activation energy for crystallization was calculated to be 2.6 eV, which is in excellent agreement with those obtained for low-temperature solid-phase crystallization.

High-mobility hydrogenated polycrystalline In2O3 (In2O3:H) thin-film transistors

Oxide semiconductors have been extensively studied as active channel layers of thin-film transistors (TFTs) for electronic applications. However, the field-effect mobility (μFE) of oxide TFTs is not sufficiently high to compete with that of low-temperature-processed polycrystalline-Si TFTs (50–100 cm2V−1s−1). Here, we propose a simple process to obtain high-performance TFTs, namely hydrogenated polycrystalline In2O3 (In2O3:H) TFTs grown via the low-temperature solid-phase crystallization (SPC) process. In2O3:H TFTs fabricated at 300 °C exhibit superior switching properties with µFE = 139.2 cm2V−1s−1, a subthreshold swing of 0.19 Vdec−1, and a threshold voltage of 0.2 V. The hydrogen introduced during sputter deposition plays an important role in enlarging the grain size and decreasing the subgap defects in SPC-prepared In2O3:H. The proposed method does not require any additional expensive equipment and/or change in the conventional oxide TFT fabrication process. We believe these SPC-grown In2O3:H TFTs have a great potential for use in future transparent or flexible electronics applications.

Nondegenerate Polycrystalline Hydrogen-Doped Indium Oxide (InOx:H) Thin Films Formed by Low-Temperature Solid-Phase Crystallization for Thin Film Transistors.

We successfully demonstrated a transition from a metallic InOx film into a nondegenerate semiconductor InOx:H film. A hydrogen-doped amorphous InOx:H (a-InOx:H) film, which was deposited by sputtering in Ar, O2, and H2 gases, could be converted into a polycrystalline InOx:H (poly-InOx:H) film by low-temperature (250 °C) solid-phase crystallization (SPC). Hall mobility increased from 49.9 cm2V−1s−1 for an a-InOx:H film to 77.2 cm2V−1s−1 for a poly-InOx:H film. Furthermore, the carrier density of a poly-InOx:H film could be reduced by SPC in air to as low as 2.4 × 1017 cm−3, which was below the metal–insulator transition (MIT) threshold. The thin film transistor (TFT) with a metallic poly-InOx channel did not show any switching properties. In contrast, that with a 50 nm thick nondegenerate poly-InOx:H channel could be fully depleted by a gate electric field. For the InOx:H TFTs with a channel carrier density close to the MIT point, maximum and average field effect mobility (μFE) values of 125.7 and 84.7 cm2V−1s−1 were obtained, respectively. We believe that a nondegenerate poly-InOx:H film has great potential for boosting the μFE of oxide TFTs.

Nucleation-controlled low-temperature solid-phase crystallization for Sn-doped polycrystalline-Ge film on insulator with high carrier mobility (∼550 cm2/V s)

High-speed thin-film transistors (TFTs) are required to develop the next generation of electronics, such as three-dimensional large-scale integrated circuits and advanced system-in-displays. For this purpose, high-carrier-mobility semiconductor films on insulator structures should be fabricated with low-temperature processing conditions (≤500 °C). To achieve this, we investigate solid-phase crystallization of amorphous-GeSn (a-GeSn) films (Sn concentration: 2% and thickness: 50–200 nm) on insulating substrates, where thin a-Si under-layers (thickness: 0–20 nm) are introduced between a-GeSn films and insulating substrates. The GeSn films are polycrystallized by annealing (450 °C, 20 h) for all samples irrespective of a-GeSn and a-Si thickness conditions, while the Si films remain amorphous. Analysis of crystal structures of GeSn films (thickness: 50 nm) reveals that grain sizes decrease from ∼10 μm to 2–3 μm by the introduction of a-Si under-layers (thickness: 3–20 nm). This phenomenon is attributed to the change in dominant nucleation sites from the interface to the bulk, which significantly decreases grain-boundary scattering of carriers through a decrease in the barrier heights at grain boundaries. Bulk-nucleation further becomes dominant by increasing the GeSn film thickness. As a result, a high carrier mobility of ∼550 cm2/V s is realized for GeSn films (thickness: 100 nm) grown with a-Si under-layers. This mobility is the largest among ever reported data for Ge and GeSn grown on an insulator. This technique will facilitate realization of high-speed TFTs for use in the next generation of electronics. At the request of the authors, this article is being retracted effective 11 July 2018.

High carrier mobility of Sn-doped polycrystalline-Ge films on insulators by thickness-dependent low-temperature solid-phase crystallization

To realize the advanced thin-film transistors (TFTs), high-carrier-mobility semiconductor films on insulator structures should be fabricated with low-temperature processing conditions (≤500 °C). To achieve this, we investigated the solid-phase crystallization of amorphous-GeSn films on insulating substrates under a wide range of Sn concentrations (0%–20%), film thicknesses (30–500 nm), and annealing temperatures (380–500 °C). Our results reveal that a Sn concentration close to the solid solubility of Sn in Ge (∼2%) is effective in increasing the grain-size of poly-GeSn. In addition, we discovered that the carrier mobility depends on the film thickness, where the mobilities are determined by the counterbalance between two different carrier scattering mechanisms. Here, vacancy-related defects dominate the carrier scattering near the insulating substrates (≤∼120 nm), and grain-size determined by bulk nucleation dominates the grain-boundary scattering of thick films (≥∼200 nm). Consequently, we obtained the maximum mobilities in samples with a Sn concentration of 2% and a film thickness of 200 nm. The effect of increasing the grain-size of poly-GeSn by lowering the annealing temperature was also clarified. By combining these results, a very high carrier mobility of 320 cm2/Vs was obtained at a low temperature of 380 °C. This mobility is about 2.5 times as high as previously reported data for Ge and GeSn films grown at low temperatures (≤500 °C). Our technique therefore opens up the possibility of high-speed TFTs for use in the next generation of electronics.

Seeding Effects of Sn/a-Ge Island Structures for Low-Temperature Lateral-Growth of a-GeSn on Insulator

Position control of low-temperature solid-phase crystallization in amorphous-GeSn (a-GeSn) films is investigated using a-GeSn films covering Sn/a-Ge stacked islands on insulator. Two-steps annealing has been performed, i.e., first-step annealing (∼250°C) to crystallize Sn/a-Ge islands for crystalline-seed formation and second-step annealing (≤250°C) to proceed lateral-growth from the crystalline-seed. It is found that Sn thickness exceeding ∼70% of Ge thickness is the essential condition to achieve crystalline GeSn islands (grain size >10 nm) with the diamond structure. This acts as crystalline-seed enabling the lateral-growth of a-GeSn over 80 μm. The present process below the softening-temperature (∼300°C) of plastic substrates facilitates realization of advanced flexible electronics.

High hole mobility tin-doped polycrystalline germanium layers formed on insulating substrates by low-temperature solid-phase crystallization

We investigated the effects of incorporation of 0%–2% tin (Sn) into amorphous germanium (Ge) on its crystallization behavior and electrical properties. Incorporation of only 0.2% Sn caused the polycrystallization temperature of Ge to lower from 450 to 430 °C, while a polycrystalline Ge1−xSnx layer with high crystallinity compared to that of polycrystalline Ge was formed by incorporation of 2% Sn. A polycrystalline Ge1−xSnx layer with a low Sn content of 2% annealed at 450 °C exhibited a Hall hole mobility as high as 130 cm2/V s at room temperature even though it possessed a small grain size of 20–30 nm. The Hall hole mobility of a poly-Ge1−xSnx layer with an Sn content of 2% was four times higher than that of a polycrystalline Ge layer and comparable to that of single-crystalline silicon.

Indentation-induced low-temperature solid-phase crystallization of Si1−xGex (x=–1) on insulator

Indentation-induced solid-phase crystallization (SPC) was proposed to achieve low-temperature growth of Si1−xGex (x=0–1) on insulator. Crystal nucleation was enhanced at the indented positions due to the stress effect, which triggered the lateral SPC. As a result, large Si1−xGex (x=0–1) crystal regions (>2 μm) were achieved on insulator at low temperatures (<590 °C). The growth kinetics for this catalyst metal-free process, i.e., activation energies for nucleation and lateral growth, are presented as a function of the Ge fraction (x).

Low-temperature solid-phase crystallization of amorphous SiGe films on glass by imprint technique

Low-temperature (<500°C) solid-phase crystallization (SPC) of amorphous Si1−xGex (x: 0–0.7) films was examined on insulating substrates by using Ni-imprint technique. Incubation time for SPC was remarkably reduced by catalytic effects without changing growth velocity. As a result, Ni-free large SiGe grains (∼4μm) were obtained at controlled positions. The crystallinity of the grown regions was almost the same as that of poly-SiGe formed by the conventional high temperature SPC at 600°C.

WITHDRAWN: Low-temperature solid-phase crystallization of amorphous SiGe films on glass by imprint technique

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Low Temperature Crystallization of a-SiGe on Insulating Films for Thin Film Transistor Application

Development of high-mobility semiconductors is strongly needed to realize high-performance thin-film transistors. To achieve this, we have been investigating low temperature solid-phase crystallization and metal-induced lateral crystallization of a- SiGe on insulating substrates. These realize uniform crystal growth of SiGe with all Ge fractions. In addition, thin-film transistors with Schottky source and drain structures were fabricated, which showed good ambipolar operation characteristics. Present paper reviews such our recent progress of low temperature SiGe growth and discusses the possible application to thin-film transistors with high speed operation.

Low-temperature solid-phase crystallization of amorphous silicon thin films deposited by rf magnetron sputtering with substrate bias

The crystallization properties of amorphous silicon (a-Si) thin film deposited by rf magnetron sputter deposition with substrate bias have been thoroughly characterized. The crystallization kinetics for films deposited with substrate bias is enhanced relative to unbiased a-Si by films. The enhanced crystallization for substrate biased a-Si films are attributed to ion enhanced nucleation of crystallites during sputter deposition which subsequently grow during the postdeposition anneal. Conversely films sputter deposited without substrate bias have more intrinsic defects and residual oxygen which enhance nucleation and retard growth, respectively, and lead to a large number of small crystallites.

Ge-enhanced MILC velocity in a-Ge/a-Si/SiO 2 layered structure

Ni-mediated low-temperature solid-phase crystallization in a-Ge/a-Si/SiO 2 layered structure has been investigated. Crystal nucleation was initiated in the a-Ge layer, which stimulated the bond rearrangement in a-Si. This enhanced lateral crystallization velocity of a-Si three times greater than that of a-Si/SiO 2 single structure. As a result, poly-Si films with large areas (∼10 μm for 5 h and ∼30 μm for 15 h) were obtained after 550 °C annealing. This will be a powerful tool for realizing large poly-Si areas on insulating films for system-in-displays and three-dimensional ultra-large-scale integrated circuits.

Enhancement of bulk nucleation in a-Si 1− xGe x on SiO 2 for low-temperature solid-phase crystallization

Nucleation phenomena in a-Si 1− x Ge x films on SiO 2 were examined in order to achieve low-temperature solid-phase crystallization. First, film thickness dependence of nucleation was investigated. The nucleation frequency per unit area increased with increasing film thickness, which was attributed to that bulk nucleation was dominant compared with interface or surface nucleation. Next, in order to enhance bulk nucleation in thin films, effects of the initial amorphicity modulation induced by Ar + irradiation (25 keV, 1×10 16 cm −2) before annealing were investigated. The incubation time for nucleation in pre-irradiated samples during subsequent annealing at 600 °C was significantly decreased to 1/20 of that without pre-irradiation, which was tentatively assigned to enhancement of atomic arrangement induced by densification of a-Si 1− x Ge x films. It is expected that optimization of the irradiation conditions will realize low-temperature (<500 °C) formation of poly-Si 1− x Ge x films on SiO 2.

Suppression of boron TED by low temperature SPC anneal prior to dopant activation

The application of a low temperature solid phase crystallization (SPC) anneal to nonpreamorphized junctions prior to a high-temperature dopant activation anneal is proposed. The SPC anneal eliminates implantation-induced defects which give rise to transient enhanced diffusion (TED), and thus reduce both vertical and lateral boron diffusion by 16 nm and 24 nm, respectively, in a conventional CMOS process thermal budget. Improved short channel effect (SCE) immunity was demonstrated with sub-100 nm FETs.