Abstract
The application of a low temperature solid phase crystallization (SPC) anneal to nonpreamorphized junctions prior to a high-temperature dopant activation anneal is proposed. The SPC anneal eliminates implantation-induced defects which give rise to transient enhanced diffusion (TED), and thus reduce both vertical and lateral boron diffusion by 16 nm and 24 nm, respectively, in a conventional CMOS process thermal budget. Improved short channel effect (SCE) immunity was demonstrated with sub-100 nm FETs.
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