Low-temperature Polycrystalline Silicon Thin-film Transistors Research Articles

Reduction of short-time image sticking in organic light-emitting diode display through transient analysis of low-temperature polycrystalline silicon thin-film transistor

Accurate compensation operation of low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) in pixel circuits is crucial to achieve steady and uniform luminance in organic light-emitting diode (OLED) display panels. However, the device characteristics fluctuate over time due to various traps in the LTPS thin film transistor and at the interface with the gate insulator, resulting in abnormal phenomena such as short-time image sticking and luminance fluctuation, which degrade display quality during image change. Considering these phenomena, transient analysis was conducted through device simulation to optimize the pixel compensation circuit. In particular, we analyzed the behavior of traps within LTPS TFT in correlation with compensation circuit operation, and based on this, proposed a methodology for designing a reset voltage scheme for the driver TFT to reduce the image sticking phenomenon.

Reducing Leakage Current Using LTPS-TFT Pixel Circuit in AMOLED Smartwatch Displays

This work proposes a new pixel circuit that is operated at a low frame rate using low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) for use in active-matrix organic light-emitting diode (AMOLED) smartwatch displays. The proposed circuit uses a new leakage-prevention method (LPM) to balance the off currents at the gate node of the driving TFTs, eliminating the drop of the driving voltage. Uniform OLED currents are thus generated throughout the extended emission period. Also, the OLEDs are all turned off except in the emission stage to suppress image flicker. To confirm the feasibility of the proposed pixel circuit, a 1.41-inch panel, based on the proposed circuit, is fabricated. Experimental results demonstrate that diminishing the off currents maintains the driving capability of the pixel circuit to stabilize the luminance of the fabricated panel. The exhibitions of red, green, blue, and white images at frame rates from 60 Hz to 15 Hz are uniform, verifying that the proposed pixel circuit with LPM has high potential for use in AMOLED smartwatch displays with a low frame rate.

Performance and reliability enhancement of flexible low-temperature polycrystalline silicon thin-film transistors via activation-annealing temperature optimization

The high performance and reliability of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) on flexible substrates need to be ensured for the proper operation of advanced flexible organic light-emitting diode (OLED) displays. However, due to the heat-sensitive components of flexible LTPS TFTs, their fabrication process faces challenges in the temperature management of its thermal treatment procedures such as activation annealing, which is an essential step in the in-line fabrication process of LTPS TFTs for activating dopants and reducing silicon lattice-related structural defects. In this work, we investigate the optimization of the activation-annealing process through the modulation of its process temperature. As the activation-annealing temperature was increased from 320 °C to 370 °C, the electrical characteristics and reliability of flexible LTPS TFTs improved owing to a decrease in the gate dielectric/channel interface and bulk channel defects. However, as the temperature was further increased to 420 °C, considerable degradations in device performance and reliability were observed due to a significant increase in the deep-level gate dielectric/channel interface and bulk channel defects. Physical analysis revealed that significant dehydrogenation, in which the breakage of Si−H bonds causes excess Si dangling bonds, occurred at 420 °C. This work shows that a fine temperature optimization of the activation annealing process is a necessary procedure for ensuring highly performant and reliable LTPS TFTs on flexible substrates.

A novel LTPO AMOLED pixel circuit and driving scheme for variable refresh rate

This paper proposes a novel pixel circuit and driving scheme that adopts low-temperature polycrystalline silicon and oxide thin-film transistors (LTPO TFTs) for mobile devices using active-matrix organic light-emitting diode (AMOLED) displays. The proposed pixel circuit and driving scheme provide uniform luminance and render flicker invisible at variable refresh rates (VRRs) from 1 to 120 Hz. Using the proposed pixel circuit with extended compensation time (tCOMP) improves the luminance uniformity at a high-frame rate. The proposed driving scheme applies a voltage to the driving TFTs (D-TFTs) higher than the programmed data voltage during the skip frame. This reduces the flicker caused by the hysteresis of D-TFTs during low-frame rate driving. A 6.0-inch quad high-definition (QHD) LTPO-based AMOLED display was fabricated using the new pixel circuit and driving scheme. Experimental results of the proposed pixel circuit show that the standard deviation of luminance was reduced from 0.056 to 0.008 by extending tCOMP from 2 to 8 µs. The flicker level was −51 dB, so there was no visual artifact during 1 Hz driving. A flicker-free LTPO-based AMOLED display with low power consumption is possible; driving can proceed in 1–120 Hz range.

Abnormal Degradation Behaviors Under Negative Bias Stress in Flexible p-Channel Low-Temperature Polycrystalline Silicon Thin-Film Transistors After Laser Lift-Off Process

This work investigates the abnormal phenomena that are observed in electrical characteristics under negative bias stress (NBS) in flexible p-channel low-temperature polycrystalline silicon thin-film transistors (p-channel LTPS TFTs) after TFTs being lifted off from a rigid substrate. During the lift-off process, mechanical strain accumulates in the buffer layer due to the unilateral force, thus resulting in the generation of defects in the buffer layer. Therefore, abnormal degradation behaviors in electrical characteristics of the lifted-off TFTs were observed during negative gate bias stress. A study on physical mechanisms is introduced to describe such abnormal phenomena, and it is confirmed that defects are produced in the buffer layer when the LTPS TFTs are lifted off. In addition, different device dimensions were discussed to support our proposed model. The findings in this work are supported by the discussion of electrical characteristics, trap state extraction, and COMSOL simulation.

High-pressure H2O post-annealing for improving reliability of LTPS and a-IGZO thin-film transistors within a coplanar structure

Improving reliability of low-temperature polycrystalline silicon (LTPS) and amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs), components of low-temperature polycrystalline silicon and oxide (LTPO), is crucial for fabricating high-performance and high-stability LTPS and oxide semiconductor-based electronics and display products. However, improving the reliability of these TFTs simultaneously in a uniform and effective manner within a coplanar structure is challenging. In this work, high-pressure H2O post-annealing (H2O HPPA) as a post-treatment for LTPS and a-IGZO TFTs within a coplanar structure are proposed to improve the uniformity and stability of the electrical characteristics simultaneously. It was demonstrated that oxygen and hydrogen in the HPPA-passivated defect state at the channel/gate dielectric layer interfaces and bulk gate dielectric layers of LTPS and a-IGZO TFTs considerably improve the uniformity and stability of the electrical performance and morphologies of the interfaces. Thus, the distribution of electrical characteristics (mobility, threshold voltage, and subthreshold swing) in LTPS and a-IGZO TFTs was reduced by more than 2-fold, and the trap charge densities at their interfaces and bulk gate dielectric layers were reduced by approximately 1.6-fold. Furthermore, the threshold voltage shift was decreased in both LTPS and a-IGZO-TFTs fabricated with H2O HPPA under negative and positive bias temperature stresses, respectively. The proposed H2O HPPA method can effectively facilitate the industry-level application of LTPS and oxide semiconductor-based electronics and display electronics.

Void-Defect Location Control of Laser-Crystallized Silicon Thin Films with Hole-Pattern

High-performance low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have been developed for larger applications than flat panel displays (FPDs) such as three-dimensional integrated circuits (3D-ICs) and glass sheet computers. The crystallinity of poly-Si thin films has been the key factor determining TFTs’ performance. In this work, a void-defect location has been controlled by patterning amorphous silicon (a-Si) thin films with rectangular and square holes before crystallized by multiline continuous-wave laser beam to avoid the effect of void-defects on the TFTs’ performance. Instead of randomly appearing in the poly-Si thin films, void-defects were only observed at the backsides of the patterned holes. Interestingly, large crystal grains without void-defects were laterally crystallized at Si strips between holes. By observing the crystallinities of poly-Si thin film around the patterned holes, both the mechanism of the void formation and crystal growth based on temperature gradient was clarified.

Electrical Characteristics of Atmospheric-Pressure Plasma Enhanced Chemical Vapor Deposition Fabricated Indium-Gallium-Zinc-Oxide Thin-Film Transistors with In-Situ Hydrogenation and Neutral Beam Oxidation

Low temperature poly-crystalline silicon thin-film transistors (LTPS-TFTs) and indium-gallium-zinc-oxide TFTs (IGZO-TFTs) are potential candidates for future technology of various displays. Due to its simple manufacturing process, low cost and good uniformity, IGZO-TFTs have been developed as main stream display technology. From the viewpoint of device electrical characteristics, a-IGZO TFTs have better field-effect mobility (>10 cm2/V * s), larger Ion/Ioff ratio (>106), smaller subthreshold swing (S.S) and good stability. In this study, atmospheric-pressure PECVD (AP-PECVD) is used to deposit a-IGZO active layer, during the deposition process In-Situ hydrogenation is applied to enhance the layer characteristics. Also, the layer is then surface oxidation treated by neutral beam system (NBS). The optimal TFTs device characteristics is reached with In-Situ hydrogenation of H2 90 sccm, and surface oxidation of 400 W NBS treatment. The field-effect mobility is 34.05 cm2/V * s, threshold voltage is 1.74 V, subthreshold swing is 62 mV/decade, and current ratio Ion/Ioff is 2.04×107. Compared with conventional plasma, NBS used in this study provides charge-free plasma which could enhance device electric characteristics.

Electrical-performance and reliability improvement of flexible low-temperature polycrystalline silicon thin-film transistors via post-annealing process

We investigated the improvement methods of the electrical characteristics and reliability of flexible low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) by optimizing the annealing process. We investigated the effect of annealing on the device properties via electrical measurement and density-of-state (DOS) analysis. The annealing temperature should be reduced for flexible LTPS TFTs compared to rigid devices because the range of the thermal stability of flexible substrate is narrower than that of the glass substrate. As the activation annealing temperature (T a) decreased, the threshold voltage and field-effect mobility (μ FE) decreased, and the subthreshold swing (SS) increased. When the post-annealing temperature (T pa) decreased, μ FE increased, and the changes in the other parameters were negligible. The DOS decreased with an increase in T a and a reduction in T pa. These results originated from ineffective dopant activation and defect curing due to the lower T a and the enhanced hydrogen defect passivation at the lower T pa. Therefore, flexible LTPS TFTs with reduced T a values exhibited similar μ FE values and lower SS values when the post-annealing process was omitted. Furthermore, removing the post-annealing process improved the reliability of the flexible LTPS TFTs with reduced T a values under electrical stress. According to a hot-carrier instability analysis, defect passivation by hydrogen was more stable than defect curing with a higher T a. Consequently, although T a was low for flexible LTPS TFTs, the electrical performance and reliability could be improved by optimizing the post-annealing process.

Improvement of the low gray-level expression using hybrid pulse width modulation and pulse amplitude modulation driving method for a micro light-emitting diode pixel circuit

A novel hybrid pulse width modulation (PWM) and pulse amplitude modulation (PAM) (HPP) driving method is proposed for improving the low gray-level expression of a micro light-emitting diode (µLED) display. At the high and middle gray-levels, PWM is adopted in order to suppress the wavelength shift of µLEDs. At the low gray-level, PAM is applied when the emission time and current of µLEDs simultaneously decrease. The HPP driving method is simulated by using a simplified p-type low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT)-based µLED pixel circuit. HPP driving exhibits stable PWM and PAM operations. Furthermore, HPP driving guarantees a data voltage range approximately 14 times larger than PWM driving, thus resulting in a robust operation with a maximum error rate of 3.83% under data signal distortion. Consequently, the µLED pixel circuit adopting HPP driving improves the low gray-level expression and demonstrates a robust circuit operation.

Abnormal Two-Stage Degradation on P-Type Low-Temperature Polycrystalline-Silicon Thin-Film Transistor Under Hot Carrier Conditions

In this study, an abnormal two-stage degradation of low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) on a polyimide flexible substrate after hot carrier stress was investigated. The degradation mechanism was divided into two stages. In the first stage, the increases in capacitance in the off region and transconductance are caused by impact ionization induced electron trapping into the gate insulator (GI) at the drain edge. Furthermore, the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula>) shift in the positive direction is caused by electrons flowing back to the source side and trapping into the buffer that induces source barrier lowing. The second stage of degradation, including a <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula> shift in the negative direction and a decrease in the transconductance is caused by Joule heating induced negative bias temperature instability (NBTI). Furthermore, NBTI hardly occurs behind the pinch off in the channel and fixed oxide charge does not compensate the trapped electron at drain side which is induced in the first stage.

Suppressing Drain-Induced Barrier Lowering and Kink Effect in Low-Temperature Poly-Si TFTs Using a Partitioned Light Shield

Anomalous drain-induced barrier lowering (DIBL) is observed in n-type low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with a full light shield (LS) structure. Drain current versus gate voltage curves exhibit a threshold voltage (V_TH) shift and hump effect as the drain bias increases, and demonstrate the unsaturated output property. Because of the inherent grain boundary and grain protrusion of LTPS TFTs, considerable impact ionization occurs, thus generating electron&#x2013;hole pairs when operated at high current, leading to a floating body effect, that confers the occurrence of the kink effect. However, the unsaturated current characteristic is induced by the LS because of its coupling potential of the LS. Therefore, partitioned LS structures are proposed to further improve the DIBL and weak the kink effect.

Improvement of Strained Negative Bias Temperature Instability in Flexible LTPS TFTs by a Stress-Release Design

In this study, the negative bias temperature instability (NBTI) under mechanical strain conditions of low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with a stress-release structure was investigated. With both electrical and mechanical stresses simultaneously applied, more significant degradation behaviors will be observed in standard TFT devices because mechanical stress makes it easier to generate strain in Si–H bonds, thus benefiting the process of electrochemical reaction. By employing a stress-release shape in the poly channel, mechanical stress, which mainly accumulates at the width edge of the poly-Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface, is moved away from the main channel; thus, fewer strained Si–H bonds can participate in the electrochemical reaction compared to the standard structure. Therefore, the degradation of devices under strained NBTI is effectively mitigated, such that the reliability of the devices is enhanced. These observations were obtained using electrical characteristics and extraction of the trap state distribution.

Shear-Force Sensor With Point-Symmetric Electrodes Driven by LTPS TFT Active Matrix Backplane

In this study, we successfully demonstrated a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$700 ~\mu \text{m}$ </tex-math></inline-formula> thick shear-force sensor with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$60\times60$ </tex-math></inline-formula> high resolution array by introducing a combination of an originally developed pressure-sensing elastomer and a newly proposed taxel (tactile pixel) structure with four point-symmetric electrodes. When shear forces are applied to the sensor substrate in several directions by lifting a weight, four sets of resistances between the electrodes are read through low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) in each taxel and clear outputs corresponding to that direction can be confirmed. Furthermore, as a result of evaluating the object recognition performance of the tactile sensor by using jigs with engraved small dimples, it was confirmed that the recognized minimum size of the shape was 1.5 mm, which suggests that the spatial resolution of this sensor is superior to the human hand perception ability. Because this sensor is ultra-thin, not bulky, and potentially applicable to flexible substrates, it is quite promising as a sensor that can be mounted on the fingertip of a robot hand with multiple functions.

Investigation on operation robustness of p-type low-temperature polycrystalline silicon thin-film transistor-based micro light-emitting diode pixel circuit using pulse width modulation under component fluctuation

In this study, we have investigated the operation robustness of a p-type low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT)-based micro light-emitting diode (µLED) pixel circuit adopting pulse width modulation (PWM) under circuit component fluctuations. The wavelength shift of µLEDs, depending on the current density, was suppressed by implementing PWM. The PWM pixel circuit controlled the emission time with constant µLED current in the simulated and measured results. In addition, the wavelength shift was suppressed below 0.48% within the 10-bit grayscale range. Furthermore, the component tolerance of the pixel circuit was investigated by simulating the error rate of µLED emission time with varying threshold voltage, mobility, subthreshold swing, and capacitance. The pixel circuit exhibited a robust operation with a maximum error rate of 4.0% under a component fluctuation of ±10%. Consequently, the µLED pixel circuit adopting PWM suppressed the wavelength shift of µLEDs and demonstrated robust circuit operation under component fluctuation.

Novel channel edge doping for hump reduction in LTPS TFTs

We proposed a new channel edge doping (CED) technique for hump reduction in n-type low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) and validated it through experiments and technology computer-aided design (TCAD) simulations. The TCAD simulations indicate that the hump effect in LTPS TFTs is due to the high electron (e−) concentration (∼1016 cm−3) induced by an enhanced electric field (e-field) at the channel edge region along the width direction. In order to reduce the hump effect, we focused on decreasing the e− concentration at the channel edge. The CED process led to the selective control of the e− concentration at the channel edge. The decrease in the maximum e− concentration from 3.4 × 1016 to 2.9 × 1014 cm−3 at the channel edge using CED led to an effective reduction in the hump characteristic of LTPS TFTs. Furthermore, the CED process does not require any additional masks and is highly effective in hump reduction, rendering it beneficial for manufacturing active-matrix organic light-emitting diode displays.

AM Mini-LED Backlight Driving Circuit Using PWM Method With Power-Saving Mechanism

This paper proposes a mini-light-emitting diode (mini-LED) driving circuit that is driven by pulse width modulation (PWM) for the backlights of active-matrix (AM) liquid crystal displays (LCDs). The proposed circuit compensates for threshold voltage (V_TH) variations of low-temperature poly-crystalline silicon thin-film transistors (LTPS TFTs) and the current-resistance (I-R) rise in VSS lines to supply a stable driving current. Operating the mini-LED at the high luminous efficacy by the PWM driving method and setting only the driving TFT on the path of the driving current reduce the power consumption of the backlight. Based on a 2.89-inch LCD panel with an AMLED <inline-formula> <tex-math notation="LaTeX">$48\times48$ </tex-math></inline-formula> backlit module, the TFTs are fabricated, measured, and fitted. Simulation results show that the relative current error rates are all below 4.67&#x0025; when the V_TH of the driving TFT varies by &#x00B1;0.3 V and the VSS rises by 0.5 V. The voltage across VDD and VSS of the proposed circuit is 4.5 V lower than that of the 6T1C compensating driving circuit, so the power consumption of the circuit is at least 27.05&#x0025; lower. Therefore, the proposed driving circuit is well suitable to use in mini-LED backlit LCDs.

A Low Power and IR Drop Compensable AMOLED Pixel Circuit Based on Low-Temperature Poly-Si and Oxide (LTPO) TFTs Hybrid Technology

In this paper, an AMOLED pixel circuit based on low-temperature poly-crystalline silicon and oxide (LTPO) thin-film transistors (TFTs) hybrid technology is proposed, which features only two transistors in a serial connection with OLED. The power supply can thus be reduced by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25{\sim }30$ </tex-math></inline-formula> % in the “Always-on-Display” (AOD) mode compared with the earlier LTPO pixel circuits which usually have three transistors in the current path and need a higher supply voltage. Furthermore, in addition to a strong suppressing ability to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ th}}$ </tex-math></inline-formula> variations/shift, the proposed pixel circuit has an excellent compensation ability for current-resistance voltage drops (i.e., IR drop), which is also superior to the earlier LTPO ones where the IR drop has to be compensated externally. Therefore, the proposed LTPO pixel circuit is able to provide AMOLED displays with lower power consumption and higher display performance than the earlier ones.

Abnormal threshold voltage shifts in p-channel low temperature polycrystalline silicon TFTs under deep UV irradiation

The electrical properties of p-channel low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) under deep ultraviolet (UV) irradiation were studied. Characteristics including threshold voltage (Vth), hole field effect mobility (μeff) subthreshold swing (SS), and leakage current (Ioff) were investigated as a function of UV irradiation doses from 4 to 20 J/cm2. With an increase in UV irradiation dosage, the Vth shift of the TFT showed a turnaround effect, which first shifted to the positive direction and then shifted back to the negative direction after a UV irradiation dose of 16 J/cm2. The continuous degradation of SS and μeff was discovered with the enhancement of UV irradiation dose. To better understand the physical mechanisms underlying these characteristic changes, UV induced traps at poly-Si grain boundaries, traps at the poly-Si and gate oxide insulator (poly-Si/SiO2) interface, and trapped charges in the gate oxide were studied with a function of UV irradiation doses.

Extremely foldable LTPS TFT backplane using blue laser annealing for low‐cost manufacturing of rollable and foldable AMOLED display

AbstractThe crystallization of a‐Si by blue laser annealing (BLA) is introduced for low‐cost, high‐resolution thin‐film transistor (TFT) backplanes for foldable and rollable AMOLED displays. A big advantage of BLA is to provide low‐temperature polycrystalline silicon (LTPS) with protrusion‐free active channel. The BLA LTPS TFT manufactured on flexible substrate exhibits high field‐effect mobility of 169 cm2/Vs, a smaller subthreshold voltage swing less than 201 mV/dec, and excellent electrical stability and mechanical robustness.