Low-temperature Polycrystalline Silicon Thin-film Transistors Research Articles

Improvement on performance and reliability of TaN/HfO 2 LTPS-TFTs with fluorine implantation

In this paper, we demonstrate the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with TaN metal-gate and HfO 2 gate dielectric to achieve high performance characteristics. A high performance LTPS-TFT with low threshold voltage 0.9 V, excellent subthreshold swing 0.15 V/decade and high I on/ I min current ratio 1.9 × 10 6 are derived without any hydrogen treatment. In addition, we also introduce the fluorine implantation prior to the Si thin-film crystallization to passivate the defects in grain-boundaries of the channel film and HfO 2/polysilicon interface. Significant improvements on subthreshold swing and I min are observed. In addition, the transconductance degradation and threshold voltage instability due to hot carrier stress is also investigated, respectively. Finally, we derive a high reliability and performance LTPS-TFT with low threshold voltage ∼1.38 V, ultra-low subthreshold swing 0.132 V/decade and high I on/ I min current ratio 1.21 × 10 7, which is suitable for the application of system-on panel (SOP).

Hot-Carrier-Induced Degradation under Current Saturation Bias in p-Channel Low-Temperature Polycrystalline Silicon Thin-Film Transistors

A two-dimensional (2-D) physical model of p-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) was proposed to analyze hot-carrier degradation based on a 2-D device and process simulator. It is found that, for current saturation bias, the maximum 2-D lateral electric field is located in the deep drain region under the gate. It can be predicted from the 2-D device simulation and experimental results that hot-electron trapping at both upper and bottom interfaces can contribute to hot-carrier degradation under current saturation stress. The degradation will first occur in a high-field region in the p+ drain region, and, with the increase in stress time, the electron-trapped region expands mainly toward the channel. For high-|Vd| bias, a decrease in impact ionization due to the presence of the trapped charges will reduce the drain current, resulting in the reduction in kink current. In low-|Vd| bias, the current flow after the long-time stress is located at the upper and bottom interfaces near the drain junction due to trapped electrons and the trapped charges at both interfaces will result in the enhancement of the Vg–Id characteristics.

High-Performance Polycrystalline-Silicon TFT by Heat-Retaining Enhanced Lateral Crystallization

High-performance low-temperature polycrystalline-silicon thin-film transistors (TFTs) have been fabricated by heat-retaining enhanced crystallization (H-REC). In the H-REC technology, a heat-retaining capping layer (HRL) is applied on the prepattern amorphous silicon islands to slow down the heat dissipation effectively. It thereby retains long duration of melting process and further enhances poly-Si-grain lateral growth. With a single shot of laser irradiation, the location-controllable poly-Si active layer with 7-mum length of grain size can be formed successfully. In addition, in this letter, the H-REC poly-Si TFT with dual gates is studied to enhanced electrical performance and stability.

An active‐matrix organic light‐emitting‐diode pixel circuit for the compensation of I × R voltage drop in power line

Abstract— A new voltage‐driving active‐matrix organic light‐emitting diode (AMOLED) pixel circuit is proposed to improve the display image‐quality of AMOLED displays. Because OLEDs are current‐driven devices, the I × R voltage drop in the power lines is evitable. Accordingly, the I × R voltage‐drop compensation scheme should be included in the pixel‐driving method when a voltage‐compensation method is used. The proposed pixel was designed for the compensation of an I × R voltage drop in the power lines as well as for the compensation of the threshold‐voltage non‐uniformity of low‐temperature polycrystalline‐silicon thin‐film transistors (LTPS TFTs). In order to verify the compensation ability of the proposed pixel, SPICE simulation was performed and compared with those of other conventional pixels. When the Vss voltage varies from 0 to 1 V, the drain current of the proposed pixel decreased by under 1% while that of conventional Vth compensation methods without Vss compensation decreased by over 60%. 2.2‐in. QCIF+ full‐color AMOLED displays, which employ the proposed pixel, have been also developed. It was verified by comparison of the display image quality with a conventional panel that our proposed panel successfully overcame the voltage‐drop problems in the power lines.

Statistical study on the temperature dependence of the turn-on characteristics for p-type LTPS TFTs

In recent years, low temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) has been widely investigated for various applications to system-on-panel (SOP) technology. However, due to the complexity of grain boundary trap properties, the conducting behaviors of various LTPS TFTs are difficult to be analyzed systematically. In this paper, the common and device-dependent thermal effects are studied to understand the conduction mechanism in the LTPS TFTs.

Reliability of Low Temperature Polycrystalline Silicon Thin-Film Transistors with Ultrathin Gate Oxide

We analyzed the reliability against the hot-carriers effect and Joule heating effects of low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with an ultrathin gate oxide film deposited by sputtering. For the hot-carrier effect, although the generation of hot-carriers was enhanced in TFT with a thin gate oxide film, no marked degradation due to direct constant voltage (DC) stress was observed in the electric characteristics even when the thickness of the gate oxide film was 9.5 nm. Regarding the effect of Joule heating on the reliability, the thickness of the oxide film markedly affected the TFT characteristics. A new degradation mode different from the conventional mode with a shift in threshold voltage owing to heat generation was observed when the oxide film was extremely thin in spite of small amount of heat generated during the application of DC stress. Regarding the reliability of the low-temperature poly-Si TFT with an ultrathin gate oxide film, the results revealed that a new degradation mode develops due to heat generation.

Embedded TFT nand-Type Nonvolatile Memory in Panel

A new NAND-type nonvolatile memory with a field-enhancing tip structure embedded in low-temperature polycrystalline silicon (LTPS) panel was demonstrated on a glass substrate for the first time. A thin-film transistor (TFT) metal-oxide-nitride-oxide-silicon (MONOS) device based on sequential lateral solidification crystallization with a fully depleted poly-Si channel, an oxide-nitride-oxide stack gate dielectric, and a metal gate is integrated into a NAND array. A NAND test array based on p-channel LTPS TFTs exhibits good cycling endurance and data retention properties and negligible program and read disturbance. These results strongly support the claim that this TFT-MONOS device is a promising candidate for use in embedded nonvolatile memory for system-on-panel and 3-D IC applications

Degradation of the Capacitance-Voltage Behaviors of the Low-Temperature Polysilicon TFTs under DC Stress

In this paper, the degradation of n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under dc stress is investigated with measurement of the capacitance between the source and the gate , as well as the capacitance between the drain and the gate . It is discovered that the degradation in curves of the device after hot carrier stress shows apparent frequency dependence, while that in the curves remains almost the same. A circuit model based on the channel resistance extracted from the current-voltage behavior is proposed to describe the frequency dependence of the capacitance behavior. From this model, it is revealed that the anomalous frequency-dependent capacitance-voltage characteristics may simply reflect the transient behaviors of the channel resistances. Besides, it was found that the curves after self-heating effect exhibit a significant shift in the positive direction and an additional increase for the smaller gate voltage, while the curves show only positive shifts. By employing simulation, it was proved that the self-heating effect creates interface states near the source region and increases the deep states in the poly-Si film near drain. The proposed circuit model further explains the behavior of the and curves for the stressed device at different measuring frequencies.

A Reliability Model for Low-Temperature Polycrystalline Silicon Thin-Film Transistors

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We proposed here a reliability model that successfully introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design. </para>

24.2: A 1300‐dpi Optical Image Sensor Using an a‐Si:H Photo Diode Array Driven by LTPS TFTs

AbstractWe have developed a 1300‐dpi optical image sensor using a hydrogenated amorphous silicon (a‐Si:H) pin diode array driven by low‐temperature polycrystalline silicon (LTPS) thin film transistors (TFT) on a glass substrate. This paper describes a new architecture for achieving a high‐resolution optical image sensor using LTPS TFT production equipment.

Stress-induced width-dependent degradation of low-temperature polycrystalline silicon thin-film transistor

This study characterizes the stress-induced subthreshold degradation effect in low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) formed using sequential lateral solidified (SLS) crystallization on a glass substrate. The SLS process is adopted to improve carrier mobility by increasing the grain size. The deterioration of the innate subgrain boundaries that are induced by channel hot-electron stress causes these transistors to exhibit double-hump subthreshold characteristics which become more prominent as the width of the channel increases. A physical theory and a proposed transistor network model accurately explain and predict the width-dependent subthreshold degradation characteristics of these stress LTPS-TFTs.

Suppression of Self-Heating in Low-Temperature Polycrystalline Silicon Thin-Film Transitors

We investigated the structure of low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) focusing on their immunity against thermal degradation. Their operating temperature was simply dependent on input power and independent of bias voltage, such as drain or gate bias voltage. As for the structures, self-heating was suppressed by increasing the number of splitting gates and the interval between poly-Si layers owing to effective heat diffusion along the gate width. For multi gate-type TFTs, increasing the number of splitting gates was effective in suppressing self-heating; however, increasing the interval between gates was not effective. We proposed a new offset-type structure. Using this new structure, we were able to demonstrate the effective suppression of degradation caused by self-heating.

Investigation of source-follower type analog buffer using low temperature poly-Si TFTs

A new source follower circuit using low-temperature polycrystalline silicon thin film transistors (LTPS-TFTs) as analog buffer for the integrated data driver circuit of active matrix liquid crystal displays (AMLCDs) and active matrix light emitting diodes (AMOLEDs) is proposed and measured. Threshold voltage compensation circuit with two n-type thin film transistors, a capacitor, and four switches structure is used to enhance image quality for the display. The threshold voltage difference of driving TFTs and the unsaturated of output voltage are eliminated in this circuit. An active load is added and a calibration operation is applied to study the effects on the source follower circuit, the transistor operation mode region is also discussed. The proposed circuit is capable of minimizing the variation from both the signal timing and the device characteristics through the simulation and measured results.

A Novel LTPS-TFT Pixel Circuit Compensating for TFT Threshold-Voltage Shift and OLED Degradation for AMOLED

This letter presents a novel pixel circuit that uses low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) composed of one driving and four switching TFTs for active-matrix organic light-emitting diodes (AMOLEDs) with a voltage-source method. The proposed circuit effectively enables threshold-voltage-shift correction of the drive TFT and compensates for degradation of the OLED using a feedback structure

Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

The authors have proved that negative bias temperature instability (NBTI) is an important reliability issue in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The measurements revealed that the threshold-voltage shift is highly correlated to the generation of grain-boundary trap states. Both these two physical quantities follow almost the same power law dependence on the stress time; that is, the same exponential dependence on the stress voltage and the reciprocal of the ambient temperature. In addition, the threshold-voltage shift is closely associated with the subthreshold-swing degradation, which originates from dangling bond formation. By expanding the model proposed for bulk-Si MOSFETs, a new model to explain the NBTI-degradation mechanism for LTPS TFTs is introduced

Plasma-Induced Damage on the Performance and Reliability of Low-Temperature Polycrystalline Silicon Thin-Film Transistors

We have investigated the impact of plasma-induced damage on the performance and reliability of low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The LTPS TFTs having different antenna structures were used to study the effects of the plasma-etching process. We observed that performance instability occurred for the devices having a relatively large-area antenna. Plasma damage mainly caused nonuniform distribution of the threshold voltages in the LTPS TFTs, presumably because of charge trapping in the gate dielectric during the plasma-etching process. The reliabilities of the LTPS TFTs having larger antenna areas were found to be more degraded under gate-bias stress and hot-carrier stress than those of the samples having smaller antenna areas. Because of their enhanced plasma damage, we speculate that the LTPS TFTs having larger antenna areas possess more trap states in the gate dielectrics. During gate-bias stress or hot-carrier stress, therefore, charges can be injected into the gate dielectric through trap-assisted tunneling, resulting in significant degradation of both the performance and reliability.

Periodically Lateral Silicon Grains Fabricated by Excimer Laser Irradiation with a-Si Spacers for LTPS TFTs

Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) with a periodic lateral silicon grain structure have been demonstrated to exhibit high-performance electrical characteristics via the amorphous silicon spacers above the amorphous silicon film crystallized with excimer laser. Amorphous silicon spacers allowed the bottom of the under-layered amorphous silicon film to serve as seed crystals. The periodic grain structure could be artificially controlled via the super lateral growth phenomenon during excimer laser irradiation. Consequently, such periodically large and lateral grains in the TFTs would achieve high field-effect-mobility of , as compared with the conventional ones of . In addition, the uniformity of device-to-device could be improved due to this location-manipulated lateral silicon grains.

Plasma Damage-Enhanced Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in LTPS TFTs. That is, when performing the NBTI measurement, the LTPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the LTPS TFT circuitry design.

A Simple Method for Gettering of Nickel within the NILC Polycrystalline Silicon Film Using a Gettering Substrate

Ni-metal-induced lateral crystallization (NILC) of amorphous silicon (α-Si) has been employed to fabricate high-performance low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs). However, the current crystallization technology often leads to trapped Ni and NiSi2 precipitates, thus degrading the device performance. We proposed using α-Si- coated wafers as gettering substrates. By bonding the gettering substrate and NILC poly-Si film together, the Ni- metal impurity within the NILC poly-Si film was greatly reduced.

Threshold‐voltage‐compensation methods for AMOLED pixel and analog buffer circuits

Abstract— New pixel‐circuit designs for active‐matrix organic light‐emitting diodes (AMOLEDs) and a new analog buffer circuit for the integrated data‐driver circuit of active‐matrix liquid‐crystal displays (AMLCDs) and AMOLEDs, based on low‐temperature polycrystalline‐silicon thin‐film transistors (LTPS‐TFTs), were proposed and verified by SPICE simulation and measured results. Threshold‐voltage‐compensation pixel circuits consisting of LTPS‐TFTs, an additional control signal line, and a storage capacitor were used to enhance display‐image uniformity. A diode‐connected concept is used to calibrate the threshold‐voltage variation of the driving TFT in an AMOLED pixel circuit. An active load is added and a calibration operation is applied to study the influences on the analog buffer circuit. The proposed circuits are shown to be capable of minimizing the variation from the device characteristics through the simulation and measured results.