Abstract
In recent years, low temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) has been widely investigated for various applications to system-on-panel (SOP) technology. However, due to the complexity of grain boundary trap properties, the conducting behaviors of various LTPS TFTs are difficult to be analyzed systematically. In this paper, the common and device-dependent thermal effects are studied to understand the conduction mechanism in the LTPS TFTs.
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