Low-temperature Polycrystalline Silicon Thin-film Transistors Research Articles

N-채널 다결정 실리콘 박막 트랜지스터의 문턱전압 변동 보상을 위한 전압 기입 AMOLED 화소회로

본 논문에서는 n-채널 저온 다결정 실리콘 박막 트랜지스터의 문턱전압 변동을 보상할 수 있는 전압 기입 AMOLED 화소회로를 제안하였다. 제안한 6T1C 화소회로는 5개의 스위칭 박막 트랜지스터, 1개의 OLED 구동 박막 트랜지스터 및 1개의 정전용량으로 구성되어 있다. SmartSpice 시뮬레이션 결과, 구동 트랜지스터의 문턱전압이 <TEX>${\pm}0.33$</TEX> V 변동시 최대 OLED 전류의 오차율은 7.05 %이고 Vdata = 5.75 V에서 OLED 양극 전압 오차율은 0.07 %로 제안한 6T1C 화소회로가 구동 트랜지스터의 문턱전압 변동에도 균일한 OLED 전류를 공급함을 확인하였다. A novel pixel circuit that uses only n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS-TFTs) to compensate the threshold voltage variation of a OLED driving TFT is proposed. The proposed 6T1C pixel circuit consists of 5 switching TFTs, 1 OLED driving TFT and 1 capacitor. When the threshold voltage of driving TFT varies by <TEX>${\pm}0.33$</TEX> V, Smartspice simulation results show that the maximum error rate of OLED current is 7.05 % and the error rate of anode voltage of OLED is 0.07 % at Vdata = 5.75 V. Thus, the proposed 6T1C pixel circuit can realize uniform output current with high immunity to the threshold voltage variation of poly-Si TFT.

Effect of nickel concentration on source/drain series resistance and channel resistance of Ni-metal-induced crystallization thin-film transistors

The Ni-metal-induced crystallization (MIC) of amorphous Si (α-Si) has been employed to fabricate low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Most studies have focused only on reducing Ni contamination because Ni residues cause high leakage current in MIC–TFTs. Also of concern is the source/drain (S/D) series resistance, which degrades the device performance (driving ability) that might vary with the Ni concentration in MIC–TFTs. Improving the driving ability of MIC–TFTs requires a detailed understanding of how Ni residues affect S/D series resistance. This study investigates how Ni concentration affects S/D series resistance by using the transmission line method. The results of this study provide further insight into how Ni concentration and resistance are related. The results show that the S/D series resistance and channel resistance decreased with a reduction in Ni concentration in MIC poly-Si because of better crystalline quality and lower degradation of the donor concentration. This phenomenon was caused by the Ni concentration forming less NiSi2 nucleation sites to generate a large grain size; Ni atoms serve as acceptor-like dopants in silicon, which counteract with the effects of n-type doping, subsequently reducing the donor concentration in the S/D region.

A Novel LTPS-TFT Pixel Circuit to Compensate the Electronic Degradation for Active-Matrix Organic Light-Emitting Diode Displays

A novel pixel driving circuit for active-matrix organic light-emitting diode (AMOLED) displays with low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) is studied. The proposed compensation pixel circuit is driven by voltage programming scheme, which is composed of five TFTs and one capacitor, and has been certified to provide uniform output current by the Automatic Integrated Circuit Modeling Simulation Program with Integrated Circuit Emphasis (AIM-SPICE) simulator. The results of simulation show excellent performance, such as the low average error rate of OLED current variation (<0.5%) and the low average nonuniformity of OLED current variation (<0.8%) while the shift of threshold voltage of the driving poly-Si TFT and the OLED are both in the worst case ( V for TFT and V for OLED). The proposed pixel circuit shows high immunity to the threshold voltage deviation of both the driving poly-Si TFT and the OLED.

Electrical Degradation and Recovery of Low-Temperature Polycrystalline-Silicon Thin-Film Transistors With Various Metal Gate Patterns

The plasma process-induced damage (PPID) of low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) (LTPS TFTs) during metal gate manufacturing is studied in this work. Different metal gate architecture configurations were designed to reduce metal line resistance, optimize TFT driving ability, and suppress TFT leakage current by increasing metal gate thickness, modifying the TFT channel width/length, and adopting dual-gate TFT structure, respectively. Experimental results indicate the relationship of the degradation and reliability of TFT with different metal gate designs after positive-bias-temperature-instability stressing. Recovery effects against process damages are also demonstrated by post-etch treatments and gate dielectric modification. The trap-state densities are measured to investigate the PPID effects due to metal gate patterning and the passivation effects after different treatments.

Low-Temperature Polycrystalline Silicon Thin-Film Transistors Enhanced by Diode-Pumped Solid State Green Continuous-Wave Laser

A novel diode-pumped solid-state continuous-wave (CW) laser technology has been demonstrated for high-performance low-temperature polycrystalline silicon thin-film transistors (TFTs) fabrication. The CW laser-crystallized (CWC) poly-Si thin films indicated the excellent crystallinity with the flat surface morphology at grain boundary. Besides, the CW laser activation is a low-thermal budget process and can achieve the lower sheet resistance of 50 Ω/□ and uniformly redistributed dopant profiles. The n-channel CWC TFTs revealed the superior field-effect mobility reaching 505 cm2/V-s and the lower subthreshold swing as compared with the conventional excimer laser-crystallized ones.

Flexible sensing systems based on polysilicon thin film transistors technology

Flexible sensors are gaining increasing interest in a number of applications, including biomedical, food control, domotics and robotics, having very light weight, robustness and low cost. In order to improve signal-to-noise ratio, integration of readout electronics is crucial and several technologies are available for the fabrication of thin film transistors (TFTs) based circuits on flexible substrates. Among these technologies, the low temperature polycrystalline silicon (LTPS) is particularly attractive, since LTPS TFTs show excellent electrical characteristics, good stability and offer the possibility to exploit CMOS architectures. The different aspects for the direct fabrication of LTPS TFTs on polymer substrates are reviewed and the specific fabrication process adopted on ultrathin polyimide substrates is described in some detail. Then, as examples of flexible sensing systems, we present both chemical and physical sensors integrated with LTPS TFTs frontend electronics. The present results can pave the way to advanced flexible sensing systems, where sensors and local signal conditioning circuits can be integrated on the same flexible substrate.

Performance Improvement of Low-Temperature Polycrystalline Silicon Thin-Film Transistors with Fluorinated Silicate Glass Drive-In Masking Layer

This study investigated a low-temperature polycrystalline silicon thin-film transistor (LTPS TFT) with a fluorinated silicate glass (FSG) drive-in masking layer on the channel layer to improve the device's performance. The FSG layer can also be patterned as a masking layer to define the source and drain (S/D) regions, and the activation of S/D regions and fluorine passivation treatment can be accomplished simultaneously. Fluorine atoms can diffuse from the FSG drive-in masking layer into the bulk channel to passivate the trap states, resulting in a considerable improvement of the electrical characteristics of the device. This demonstrated that the field-effect mobility increased from 10.9 to 30.4 cm2 V-1 s-1, and the on/off current ratio increased from 8.9 ×104 to 10.4 ×105. The proposed scheme is simple, economical, and suitable for mass production of large-sized displays.

Voltage Driving Scheme Using Three TFTs and One Capacitor for Active-Matrix Organic Light-Emitting Diode Pixel Circuits

This work presents a new active-matrix organic light-emitting diode (AMOLED) pixel circuit with a novel driving scheme that is based on low-temperature polycrystalline-silicon thin film transistors (LTPS TFTs). The proposed circuit that consists of one driving TFT and two switching TFTs, which are all p-type, can successfully compensate for not only variations in the TFT threshold voltage but also the current-resistance (IR) voltage drop in the power line. The functionality of the pixel circuit for the array structure and the uniformity of organic light-emitting diode (OLED) current are verified using H-Simulation Program with Integrated Circuit Emphasis (HSPICE). According to the results of a simulation, over the entire range of tested data voltages (-4.5 to -2.5 V), the relative errors of the OLED current of the proposed circuit are below 1.2% when the driving TFT threshold voltage varies from -0.5 to +0.5 V.

Performance Improvement of Low-Temperature Polycrystalline Silicon Thin-Film Transistors with Fluorinated Silicate Glass Drive-In Masking Layer

Performance Improvement of Low-Temperature Polycrystalline Silicon Thin-Film Transistors with Fluorinated Silicate Glass Drive-In Masking Layer

Rapid determination of surface roughness of polycrystalline silicon following frontside and backside excimer laser irradiation

Excimer-laser crystallization (ELC) is the most commonly employed technology for fabricating low-temperature polycrystalline silicon (LTPS). Investigations on the surface roughness of polycrystalline silicon (poly-Si) thin films have become an important issue because the surface roughness of poly-Si thin films is widely believed to be related to its electrical characteristics. In this study, we develop a simple optical measurement system for rapid surface roughness measurements of poly-Si thin films fabricated by frontside ELC and backside ELC. We find that the incident angle of 20° is a good candidate for measuring the surface roughness of poly-Si thin films. The surface roughness of polycrystalline silicon thin films can be determined rapidly from the reflected peak power density measured by the optical system developed using the prediction equation. The maximum measurement error rate of the optical measurement system developed is less than 9.71%. The savings in measurement time of the surface roughness of poly-Si thin films is up to 83%. The method of backside ELC is suggested for batch production of low-temperature polycrystalline silicon thin-film transistors due to the lower surface roughness of poly-Si films and higher laser-beam utilization efficiency.

High-Frequency Modeling of Poly-Si Thin-Film Transistors for Low-Cost RF Applications

In this paper, we present high-frequency characteristics of transistors and inductors in low-temperature polycrystalline-silicon thin-film transistor (LTPS TFT) technology for low-cost radio frequency applications. From 2-D device simulations, we show that the linearity of LTPS TFTs is independent of the channel length due to the presence of grain boundaries. Furthermore, since LTPS TFTs can be fabricated on insulating substrates, on-chip spiral inductors on such substrates have negligible substrate loss, leading to high quality ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$Q$</tex></formula> ) factor. From electromagnetic simulations, we observe that spiral inductors in LTPS TFT technology show lower parasitics, higher <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$Q$</tex> </formula> factor, and higher self-resonance frequency <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(f_{\rm RES})$</tex> </formula> compared to typical bulk CMOS inductors having similar inductance. Such high <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$Q$</tex></formula> of inductors allows compensating for low <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$g_{m}$</tex></formula> of LTPS TFTs.

An integrated micro-manipulation and biosensing platform built in glass-based LTPS TFT technology

The glass-based low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) process, widely known for making liquid crystal displays, is utilized in this work to realize a fully integrated, microbead-based micro-manipulation and biosensing platform. The operation utilizes arrays of microelectrodes made of transparent iridium tin oxide (ITO) to move the immobilized polystyrene microbeads to the sensor surface by dielectrophoresis (DEP). Detection of remaining microbeads after a specific antigen/antibody reaction is accomplished by photo-detectors under the transparent electrodes. It was found that microbeads can be driven successfully by the 30 × 30 µm2 microelectrodes separated by 10 µm with no more than 6 Vp–p, which is compatible with the operating range of thin-film transistors. Microbeads immobilized with antimouse immunoglobulin (IgG) and prostate-specific antigen (PSA) antibody were successfully detected after specific binding, illustrating the potential of LTPS TFT microarrays for more versatile biosensing applications.

High-Performance Polycrystalline Silicon Thin-Film Transistors with Two-Dimensional Location Control of the Grain Boundary via Excimer Laser Crystallization

High-performance low-temperature polycrystalline silicon (Poly-Si) thin-film transistors (TFTs) have been fabricated with two-dimensional (2-D) location-controlled grain boundaries using excimer laser crystallization (ELC). By locally increased thickness of the amorphous silicon (a-Si) film that was served as the seed crystals with a partial-melting crystallization scheme, the cross-shaped grain boundary structures were produced between the thicker a-Si grids. The Poly-Si TFTs with one parallel and one perpendicular grain boundary along the channel direction could therefore be fabricated to reach excellent field-effect mobility of 530 cm2/V-s while the conventional ones exhibited field-effect mobility of 198 cm2/V-s. Furthermore, the proposed TFTs achieved not only superior electric properties but also improved uniformity as compared with the conventional ones owing to the artificially controlled locations of grain boundaries.

Analysis of Degradation Mechanisms in Low-Temperature Polycrystalline Silicon Thin-Film Transistors under Dynamic Drain Stress

Degradation induced by dynamic drain stress in both n-type and p-type low-temperature polycrystalline silicon thin-film transistors (TFTs) is systematically investigated. A transition-time-dependent hot-carrier (HC) mechanism is attributed to be the dominant degradation mechanism even for stress amplitudes close to the operation condition. Previously proposed nonequilibrium-drain-junction degradation model is further elaborated by including time-dependent carrier emission/recombination process. Different from that of n-type TFTs, a two-stage degradation behavior is first observed in p-type TFTs. By considering the effect of electron trapping in the initial stage on the dynamic HC mechanism in the second stage, degradation of both n-type and p-type TFTs can be consistently understood within a unified model, which also explains the absence of the two-stage degradation in n-type TFTs. Finally, this paper is further extended to show that the unified model should also be applicable to HC degradation induced by dynamic gate stress.

P‐7: A New 3‐TFT Current Scaling Pixel Circuit for AMOLED Displays

AbstractA new current scaling pixel circuit using three low‐temperature polycrystalline‐silicon (LTPS) thin‐film transistors (TFTs) for Active Matrix Organic Light Emitting Diodes (AMOLEDs) is presented. The proposed circuit with simplified components can enhance the aperture ratio, accelerate the pixel programming time, as well as compensate for the variations of TFT threshold voltage.

Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-κ Eu2O3 gate dielectrics

In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu2O3 gate dielectric. High-κ Eu2O3 LTPS-TFT annealed at 500 °C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm2/V-s, a small subthreshold swing of 142 mV/decade, and a high Ion/Ioff current ratio of 1.34 × 107. These significant improvements are attributed to the high gate-capacitance density due to the adequate quality of Eu2O3 gate dielectric with small interfacial layer of effective oxide thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu2O3 LTPS-TFT device.

Electrical Stress Effect on the Leakage Current of Metal-Induced Laterally Crystallized &lt;I&gt;p&lt;/I&gt;-Channel Poly-Si TFTs

A p-type polycrystalline silicon thin-film transistor (TFT) was fabricated using the metal-induced lateral crystallization (MILC) technique at 550 degrees C. To reduce the leakage current in the MILC TFT, electrical stress (ES), newly developed in this work, was applied prior to the I(D)-V(G) measurements. It was found that ES is effective only when the TFT is under off-state. The stress gate voltage is related to the leakage current at high gate voltages and the electric field between the source and the drain to the leakage current at low gate voltages. The leakage current of the MILC TFT could be lowered to 10(-11) A for width/length ratios of 1/2 measured at the drain voltage of 3 V. A new plausible model has been suggested to explain the ES effect on the leakage current behavior in low-temperature polycrystalline silicon TFTs.

LTPS-TFT Pixel Circuit Compensating for TFT Threshold Voltage Shift and IR-Drop on the Power Line for AMOLED Displays

We propose a new pixel design for the active matrix organic light-emitting diode (AMOLED) using low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs). The proposed pixel is composed of four switching TFTs, one driving TFT (DTFT), and one capacitor. The simulation results are performed by AIM-SPICE software. The error rate of OLED output current with (threshold voltage) variation (0.3&#x2009;V) and power line drop by 1&#x2009;V are improved to about 1.67&#x25; and 15&#x25;, respectively. Thus, the proposed pixel circuit can successfully overcome drawbacks suffered from DTFT threshold voltage deviation and IR-drop on power line.

Effect of Nickel Concentration on Bias Reliability and Thermal Stability of Thin-Film Transistors Fabricated by Ni-Metal-Induced Crystallization

Ni-metal-induced crystallization (MIC) of amorphous Si (α-Si) has been employed to fabricate low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Although the high leakage current is a major issue in the performance of conventional MIC-TFTs since Ni contamination induces deep-level state traps, it can be greatly improved by using well-known technologies to reduce Ni contamination. However, for active-matrix organic light-emitting diode (AMOLED) display applications, the bias reliability and thermal stability are major concerns especially when devices are operated under a hot carrier condition and in a high-temperature environment. It will be interesting to determine how the bias reliability and thermal stability are affected by the reduction of Ni concentration. In the study, the effect of Ni concentration on bias reliability and thermal stability was investigated. We found that a device exhibited high immunity against hot-carrier stress and elevated temperatures. These findings demonstrated that reducing the Ni concentration in MIC films was also beneficial for bias reliability and thermal stability.

The effect of gate overlap lightly doped drains on low temperature poly-Si thin film transistors

Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have a high carrier mobility that enables the design of small devices that offer large currents and fast switching speeds. However, the electrical characteristics of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects, such as large leakage currents, the kink effect, and the hot-carrier effect. For this paper, LTPS TFTs were fabricated, and the SiN x /SiO 2 gate dielectrics and the effect of the gate-overlap lightly doped drain (GOLDD) were analyzed in order to minimize these undesired effects. GOLDD lengths of 1, 1.5 and 2 μm were used, while the thickness of the gate dielectrics (SiN x /SiO 2) was fixed at 65 nm (40 nm/25 nm). The electrical characteristics show that the kink effect is reduced in the LTPS TFTs using a more than 1.5 μm of GOLDD length. The TFTs with the GOLDD structure have more stable characteristics than the TFTs without the GOLDD structure under bias stress. The degradation from the hot-carrier effect was also decreased by increasing the GOLDD length. After applying the hot-carrier stress test, the threshold voltage variation (Δ V TH) was decreased from 0.2 V to 0.06 V by the increase of the GOLDD length. The results indicate that the TFTs with the GOLDD structure were protected from the degradation of the device due to the decreased drain field. From these results it can be seen that the TFTs with the GOLDD structure can be applied to achieve high stability and high performance in driving circuit applications for flat-panel displays.