Low-temperature poly-Si Thin-film Transistors Research Articles

Extended-Gate pH Sensors Using Self-Aligned Four-Terminal Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Glass Substrate

High-performance polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) on glass substrate are applicable to high-performance and low-cost pH sensors. We previously reported on four-terminal (4T) self-aligned planar embedded metal double-gate (E-MeDG) low-temperature (LT) poly-Si TFTs on glass substrate. This device includes a metal top gate (TG) and a metal bottom gate (BG), which are fabricated from a sputtered tungsten film. The BG is embedded in the glass substrate through chemical mechanical polishing, and the TG is fabricated in a self-aligned manner to the BG by using back-surface exposure. The material of the gate dielectric is silicon dioxide (SiO2), which is deposited using plasma-enhanced chemical vapor deposition, and has a thickness of 75 and 150 nm against the TG and BG, respectively. The material of the channel region is poly-Si, which is fabricated using diode-pumped solid-state continuous-wave laser lateral crystallization. The TG and BG can be used as the drive and control gates, and vice versa. In this device, we were able to control the threshold voltage (Vth) by varying the voltage applied to the control gate, and we confirmed a high Vth controllability. This Vth controllability is applicable for pH sensors because voltage variation applied to the control gate due to a change in pH can be read as the Vthvariation of the TFTs. Therefore, the 4T self-aligned planar E-MeDG LT poly-Si TFT can be used as an extended-gate field-effect transistor (EGFET) to measure the voltage variation due to a change in pH. Thus, we performed an evaluation of pH sensors by using the 4T self-aligned planar E-MeDG LT poly-Si TFT as an EGFET. The evaluation of pH sensors was performed using a typical glass electrode, reference electrode, and pH buffer solution in addition to the 4T self-aligned planar E-MeDG LT poly-Si TFTs. The glass electrode was connected to the TG or BG of the TFTs. The reference electrode was connected to the electrode, which applied a constant voltage. The glass electrode and reference electrode were set in the pH buffer solution. In this situation, we evaluated the pH sensors by measuring the transfer characteristics of the TFTs by using another gate, which was not connected to the glass electrode, as the drive gate. In the first experiment, we connected the glass electrode to the BG and measured the transfer characteristics by using the TG as the drive gate against pH = 8.8 and pH = 4.2 buffer solutions under various reference electrode voltages. We confirmed that the transfer characteristics of the drive gate in the pH = 8.8 buffer solution shifted toward the positive direction against the characteristics in the pH = 4.2 buffer solution at every reference electrode voltage. The pH sensitivity calculated from the Vthvariation is 21.7 mV/pH, which is fairly consistent with the theoretical pH sensitivity of 25.5 mV/pH. In the second experiment, we connected the glass electrode to the TG and measured the transfer characteristics by using the BG as the drive gate against pH = 8.7 and pH = 4.8 buffer solutions at various reference electrode voltages. We confirmed that the transfer characteristics of the drive gate in the pH = 8.7 buffer solution shifted toward the positive direction against the characteristics in the pH = 4.8 buffer solution. This trend is the same as that of the top-gate drive TFT, but the pH sensitivity calculated from the Vthvariation is 76.9 mV/pH, which is larger than that of the top-gate drive TFT. In addition, its magnitude is found to be fairly consistent with the theoretical pH sensitivity of 88.8 mV/pH. We consider that the difference in pH sensitivity between the TG and BG drives is caused by the difference in thickness between the TG and BG SiO2 dielectric. We previously confirmed that the ratio of the Vthvariation against the control gate voltage variation is larger in the BG drive than in the TG drive. We consider that the difference in pH sensitivity reflects this phenomenon. Thus, the experimental results indicate that 4T self-aligned planar E-MeDG LT poly-Si TFTs can be successfully operated as pH sensors. In summary, we confirmed that 4T self-aligned planar E-MeDG LT poly-Si TFTs can be successfully operated as pH sensors. In addition, to improve the pH sensitivity of EGFETs, our experimental results indicate that the combination of the capacitance of the top and bottom gates is a significant parameter.

(Invited) Self-Aligned Four-Terminal Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Glass Substrate Using Continuous-Wave Laser Lateral Crystallization

Low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) are indispensable for applications that involve integrating high-speed and low-power dissipation complementary metal-oxide-semiconductor (CMOS) circuits onto a glass substrate. The on-current of the LT poly-Si TFTs can be enhanced by fabricating a high-quality poly-Si film on the glass substrate. In the current study, the fabrication of these transistors was achieved using continuous-wave laser lateral crystallization (CLC). This method enabled us to form a lateral poly-Si film with high quality and large grain size (the grain area was approximately 100 times larger than that of the conventional excimer-laser crystallization (ELC) poly-Si film) without damaging the substrate. A possible approach to achieve low-power dissipation is by controlling the threshold voltage (Vth). In order to control the Vth of the LT poly-Si TFTs, we fabricated self-aligned four-terminal (4T) LT poly-Si TFTs using high-quality CLC poly-Si film. These TFTs comprise metal gates on the top and bottom. The bottom metal gate was embedded in the glass substrate using a chemical mechanical polish. The top metal gate was fabricated by a self-aligned process of back surface exposure using the bottom metal gate as a photomask. This TFT was fabricated on a fused quartz glass at 550°C. The top and bottom metal gates acted as drive and control gates, respectively, or vice versa. The performance of the fabricated n-channel (n-ch) and p-channel (p-ch) self-aligned 4T CLC LT poly-Si TFTs was evaluated. To evaluate their feasibility, an E/D inverter was utilized by connecting two identical n-ch TFTs on different glass substrates, which were fabricated by identical processes.The self-aligned 4T CLC LT poly-Si TFTs showed excellent Vth controllability. The variation of the Vth of the drive gate TFT, with respect to small variation in the control gate voltage, was found to closely match the theoretically predicted values of the top and bottom gate drives for both n- and p-ch TFTs. The output characteristics of the drive TFTs were found to be sensitive to the varying magnitude of the control gate voltage. The mobility of the n-ch TFTs in the top and bottom drive TFTs was above 300 cm2/Vs. This remarkable performance may be attributed to the high-quality CLC poly-Si film. The mobility varied sensitively against the strength of the vertical electric field, which was changed by varying the control gate voltage. The s.s. values were also found to vary depending on the control gate voltage, and this variation is explained by the change in the position of the channel layer towards the side of either the drive or the control gate. By exploiting the high controllability of the 4T TFTs, an E/D inverter was fabricated and successfully operated at 2.0 V. The Vth of the self-aligned 4T CLC LT poly-Si TFTs was found to be sensitive to a 20-meV variation of the control gate voltage. Utilizing this sensitivity, we further fabricated an extended-gate pH sensor, where the control gate was connected to the glass electrodes, and the pH of the solution varied from 4.1 to 8.8. Consequently, we were able to successfully observe the variation of the drain current in the drive gate TFT depending on the strength of pH. In summary, the results suggest that the high controllability of the self-aligned 4T CLC LT poly-Si TFTs could enable us to fabricate high-speed and low-power-dissipation circuits on a glass substrate. Further, our study suggests the promising potential of such TFTs for applications involving sensor fabrication.

Charge-Trap Inactivation of Multi-Line-Beam Clc Poly-Si Tfts Using Channel Impurity Doping

Linearly-arranged long silicon crystal grains have been formed by using Multi-Line-Beam Continuous-wave laser Lateral Crystallization (MLB-CLC). Crystallinity of the laser-crystallized poly-Si thin film are biaxially oriented to (110)-(111)-(211) crystal orientation. The low-temperature poly-Si thin film transistors (LTPS-TFTs), however have a high-OFF leakage current and ON/OFF ratio become small. Charge traps on the long grain boundaries between source and drain would induce the high-OFF leakage current. In this work, we introduce a channel doping for inactivation of the traps, and high ON/OFF ratio is achieved. Poly-Si TFTs were fabricated as follows. Buffer SiO2 film (1 μm), a-Si (150 nm) and cap SiO2 (100 nm) were deposited on a quartz substrate. CW laser lateral crystallization with multi-line laser-beam spot was carried out on the a-Si films. The wavelength of the laser was 532 nm, and laser power and scan speed were 7.5 W and 0.5 cm/s, respectively. After the laser crystallization, the cap SiO2 was etched with buffered HF aqueous solution (BHF). In order to pattern the poly-Si active layer, lithography and dry etching (Cl2: 20 sccm, HBr: 20 sccm) were performed. Channel doping on channel region was carried out by boron (B) ions with 3 conditions (ion dose: 5×1012 cm-2, 7×1012 cm-2, 9×1012 cm-2, acceleration voltage: 19 keV). Gate SiO2 (42 nm) was deposited with ICP- CVD. Mo gate electrode (300 nm) was deposited by sputtering method. After resist patterning, the gate electrode was etched with an aqueous solution of H3PO4: HNO3: CH3COOH: H2O = 400: 25: 50: 25. A self-aligned S/D regions were formed by As ion doping (ion dose: 2×1015cm-2, acceleration voltage: 66 keV). Activation anneal was carried out at 550℃ in N2 ambient for 30 minutes. A sacrificial oxide layer in the S/D region was removed with BHF. After the removal, interlayer SiO2 film was deposited with APCVD. Contact holes were formed on the APCVD interlayer dielectric film with BHF. Mo metal pad was deposited by sputtering method, and finally the samples were sintered at 400°C in H2 ambient for 30 minutes. The IDS - VGS characteristic of the fabricated poly-Si TFTs are shown in Fig.1. As the boron impurity concentration increased, the off-leakage current was reduced. It is considered that boron impurity compensated the defect traps in the channel region. At the concentration of 1.3×1020 cm-3, the off leakage current at Vg=0 V was 3×10-11 A and ON/OFF ratio was 106. ON current was reduced by introducing the channel impurity. The electron field-effect mobilities for the boron impurities of 7.1×1019 cm-3, 1.0×1020 cm-3 and1.3×1020 cm-3 were 398, 333, and 261 cm2/Vs, respectively. By introducing boron impurity, the Coulomb scattering was occurred and the electron mobility was reduced. Figure 1

Characterization of (100)-Dominantly Oriented Poly-Si Thin Film Transistors Using Multi-Line Beam Continuous-Wave Laser Lateral Crystallization

Low-temperature poly-Si thin film transistors with high mobility and uniformity have been required for high resolution flat panel display (FPD) technology. In this work, we succeeded in controlling orientation of poly-Si film by using multi-line beam (MLB) continuous-wave laser lateral crystallization (CLC) with overlapping and (100)-dominantly oriented poly-Si film was realized. Si crystal grains were developed along laser scanning direction with an average grain size of approximately 20 μm x 2 μm. The adjacent Si crystal grains had almost identical orientation in the space with misorientation angle of under 15o. The fabricated TFTs have high field effect mobility up to 1010 cm2/Vs. Moreover, device characteristics of the fabricated TFTs were investigated and mobility variation was evaluated.

Crystallinity Evaluation of Low Temperature Polycrystalline Silicon Thin Film Using UV/Visible Raman Spectroscopy

Low temperature poly-Si (LTPS) is one of the most important high mobility channel materials for thin film transistors (TFTs). However, the improvement of the LTPS TFT performance is limited by the grain size and crystallinity variation. Thus, advanced nondestructive and high-resolution evaluation techniques are needed for LTPS thin film to monitor its crystallinity and grain size distribution. We evaluated the crystallinity of LTPS thin film during the fabrication process with various conditions using UV/visible Raman spectroscopy. As a result, we confirmed from Raman imaging measurements that a-Si deposited at higher temperature and lower pressure is crystallized rapidly. It can be considered that slow crystallization is caused by strong tensile strain and high hydrogen concentration in LTPS thin films. Furthermore, good crystallinity can be obtained with increasing annealing duration and deposition temperature of a-Si. In conclusion, we believe Raman spectroscopy, especially when used as imaging technique, is useful for in-line process evaluation.

Bias temperature instability comparison of CMOS LTPS-TFTs with HfO2 gate dielectric

In this paper, the positive and negative bias temperature instability (P/NBTI) of complementary metal–oxide–semiconductor (CMOS) low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are studied simultaneously. Significant threshold voltage shift ΔVTH, degradation of the subthreshold swing S.S. and transconductance Gm are observed for both n-type LTPS-TFTs after PBTI stress and p-type LTPS-TFTs after NBTI stress. Moreover, the Gm degradation rate with the stress time of p-type devices during NBTI shows significantly different behavior from the PBTI of n-type devices. The PBTI of n-type device shows a saturation behavior of the Gm degradation with various stress bias and temperature. Conversely, the NBTI of p-type device shows an enhanced Gm degradation rate with the increase of stress time and stress temperature. In addition, the threshold voltage shift |ΔVTH| of PBTI does not obey the traditional empirical power law model, but the NBTI obeys it with higher time exponent. Consequently, the NBTI of the p-type device shows worse driving current Idrv degradation than the PBTI of the n-type device mainly due to the different Gm degradation behavior.

Low power low temperature poly-Si thin-film transistor shift register with DC-type output driver

This paper demonstrates a low power DC-type low temperature poly-Si (LTPS) thin-film transistor (TFT) shift register that consists of nine TFTs and one bootstrapping capacitor. The proposed circuit connects large size pull-up TFTs of output drivers to positive supply instead of alternating clock signals in order to reduce substantially the power consumption of clock drivers. The SPICE simulation ensures that the variable overlap intervals can be programmed by the delay between clock signals and the overall power consumption of a DC-type circuit can be reduced to 45% of an AC-type one for a full-HD display. The operation of a proposed structure is also verified with a fabricated 16-stage gate driver.

(Invited) High-Performance Top-Gate and Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors Fabricated Using Continuous-Wave-Laser Lateral Crystallization on a Glass Substrate

A high-quality polycrystalline silicon (poly-Si) film is a technology for improving the performance of low-temperature (LT) poly-Si thin-film transistors (TFTs). We have already developed continuous-wave-laser lateral crystallization (CLC) using a diode-pumped solid-state laser to improve the crystalline quality of the thin poly-Si film. In this paper, we report on two approaches for improving the performance of LT poly-Si TFTs, which are based on a thin CLC poly-Si film and are fabricated at 550 ºC on a glass substrate. The first approach is a combination of a CLC poly-Si film and sputtered HfO2 as the gate dielectric. The other approach is a combination of a CLC poly-Si film and a double-gate structure for realizing four-terminal LT poly-Si TFTs. The former exhibited an enhancement in the on-current that was four times greater than a device with a silicon dioxide gate stack. In the latter, high controllability of the threshold voltage was confirmed.

Lifetime Extension Method for Active Matrix Organic Light-Emitting Diode Displays Using a Modified Stretched Exponential Decay Model

In this letter, we propose a compensation method for organic light-emitting diode (OLED) degradation occurring in a digital driving scheme for active-matrix OLED displays. The proposed method, in which we are the first to propose, employs the modified stretched exponential decay (SED) model to characterize the OLED degradation and compensates for the associated luminance decrease; the lifetime of an OLED panel can thereby be extended. The OLED panel is fabricated using low-temperature poly-Si thin-film transistors, and measured to verify the modified SED model and the proposed compensation method. The measurement results show that the luminance degradation with and without the proposed method is 0.3% and 6%, 4% and 17.8%, and 7.4% and 30.4%, for red, green, and blue OLEDs, respectively. This measurement is taken after 40 h of operation under a 350 cd/m 2 initial luminance. Accordingly, the proposed compensation method extends the lifetime of the OLED panel up to 72.5, 15.5, and 20.75 times longer in red, green, and blue OLEDs, respectively, compared with the conventional method.

Reverse Electrical Behavior of N-Channel and P-Channel LTPS-TFTs by N<sub>2</sub>O Plasma Surface Treatment

In this paper, the opposite impacts of N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O plasma surface treatment on the n- and p-channel low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric are investigated. Significant performance improvement of n-channel LTPS-TFT by N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O plasma surface treatment is observed, including threshold voltage reduction ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ~ -0.57 V, 1.55× higher transconductance G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> , and 1.82× higher driving current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">drv</sub> . However, p-channel LTPS-TFT shows serious performance degradation after N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O plasma surface treatment, including threshold voltage increase ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ~ -0.99 V, transconductance G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> reduction, and driving current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">drv</sub> degradation. The difference of the two mechanisms of N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O plasma surface treatment, namely, plasma induced interfacial layer (PIL) growth effect and trap passivation effect on poly-Si, is elaborated by a process of the PIL removal after the PIL growth. As a result, the trap passivation effect benefits both n- and p-channel LTPS-TFTs. The PIL growth effect shows the opposite impacts on the n- and p-channel LTPS-TFTs, that benefits n-channel LTPS-TFT and degrades p-channel LTPS-TFT seriously. Therefore, the negative impacts of N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O plasma surface treatment on the p-channel LTPS-TFTs can be eliminated by a PIL removal step in the process. These results would be critical for the applications of system-on-panel and 3-D integrated circuit.

Characteristics of Poly-Si Thin Film Transistors with Highly Biaxially Oriented Linearly Arranged Poly-Si Thin Films Using Double Line Beam Continuous-Wave Laser Lateral Crystallization

Highly biaxially oriented linearly arranged poly-Si thin films were formed by double line beam continuous-wave laser lateral crystallization (DLB-CLC). Crystallinities of the poly-Si thin films were (110), (111), and (211) for the laser scan, transverse, and surface directions, respectively, and energetically stable Σ3 grains boundary were observed dominantly. Silicon grains were elongated in the laser scan direction and one-dimensionally very large silicon grains with lengths of more than 100 µm were fabricated. High-performance low-temperature poly-Si thin film transistors (TFTs) using these poly-Si thin films were fabricated at low temperature (≦550 o C) by a metal gate self-aligned process.The TFTs were fabricated as follows. A-Si of 150 nm thickness and cap SiO2 of 100 nm thickness were deposited on a quartz substrate. CW laser crystallization with double-line spot irradiation (wavelength: 532 nm, laser power: 8.5 W, scan speed: 0.25 cm/s) on a-Si was carried out, and lateral-crystallized poly-Si was formed. After the laser crystallization, the cap SiO2 was etched using buffered HF aqueous solution (BHF), and lithography and dry etching (Cl2: 40 sccm, HBr: 40 sccm) were performed in order to pattern the poly-Si active layer. Next, gate SiO2 of 50 nm thickness was deposited by inductively coupled plasma chemical vapor deposition (ICP CVD, SiH4: 0.6 sccm, O2: 10 sccm, Ar: 40 sccm) and a Mo gate electrode of 200 nm thickness was deposited by sputtering method. After lithography patterning, wet etching of Mo was carried out with a solution of H3PO4: HNO3: CH3COOH: H2O= 400: 25: 50: 25 and the gate electrode was formed. A self–aligned source and drain system was formed by As ion doping (ion dose: 2×1015 cm-2, acceleration voltage: 66 keV) using the Mo gate electrode as the mask. Activation annealing treatment was carried out at 550o C in N2 ambient for 30 min. A sacrificial oxide layer in the S/D region was removed using BHF. After the removal, 150-nm-thick interlayer insulation films were deposited by atmospheric pressure chemical vapor deposition (APCVD), and the contact hole was etched using BHF. A Mo metal pad was deposited by sputtering method, and finally sintering processing was carried out at 400 o C in H2ambient for 30 min. Figure 1 shows a microphotograph of the fabricated DLB-CLC poly-Si TFT.A TFT with a high electron field effect mobility of µFE= 560 cm2V-1s-1 in a linear region was realized. At the electron field effect mobility, its variation was within 10% at same crystallization region. High-performance TFTs with DLB-CLC were demonstrated, however it was found that off-leakage current was relatively large. The leakage current mechanism was investigated by measuring temperature dependence of the TFT characteristics. The field-effect mobilities at the ON region were proportional to T-1.5 as shown in Fig. 2. The result shows the phonon scattering was dominant as same as single silicon crystal. On the other hand, in the OFF region, the electrical conductivity shows logarithmic behavior as a function of exp{-EB/kBT} as shown in Fig. 3. This leakage current shows that there are many trap states in the grain boundaries.

Characteristics of Poly-Si Thin Film Transistors with Highly Biaxially Oriented Linearly Arranged Poly-Si Thin Films Using Double Line Beam Continuous-Wave Laser Lateral Crystallization

Highly biaxially oriented linearly arranged poly-Si thin films were formed by double-line beam continuous-wave laser lateral crystallization (DLB-CLC). Crystallinities of the poly-Si thin films were (110), (111), and (211) for the laser scan, transverse, and surface directions, respectively, and an energetically stable Σ3 grain boundary was dominantly observed. Silicon grains were elongated along the laser scan direction and one-dimensionally very large silicon grains with lengths of more than 100 µm were formed. High-performance low-temperature poly-Si thin film transistors (TFTs) using these poly-Si thin films were fabricated at low-temperatures (≦550゜C) by a metal gate self-aligned process and a TFT with a high electron field effect mobility of µFE= 560 cm2V-1s-1 in a linear region was realized. Also, electron field effect mobility variation of below 10% was obtained at the same crystallization region. Leakage current mechanism was also investigated by temperature dependence of the TFT characteristics.

Distinction between interfacial layer effect and trap passivation effect of N2 plasma treatment on LTPS-TFTs

In this paper, N2 plasma surface treatment on high performance low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric is demonstrated. A significant performance improvement by N2 plasma surface treatment is observed, including the threshold voltage VTH reduction∼−0.94V, subthreshold swing S.S. improvement from 0.227V/dec. to 0.188V/dec., field effect mobility μFE enhancement∼+61% and driving current Idrv enhancement ∼+95%. The individual impacts of interfacial layer growth effect and trap passivation effect of poly-Si channel film are investigated by the plasma induced interfacial layer (PIL) removal process. The results show that the PIL growth effect has more contribution to the improvement of VTH reduction and Idrv enhancement than the trap passivation effect of poly-Si channel film. Consequently, the interfacial layer engineering would be very important for the development of high performance LTPS-TFTs.

Asymmetric Driving Current Modification of CMOS LTPS-TFTs With ${\rm HfO}_{2}$ Gate Dielectric

In this paper, the asymmetric driving current Idrv modification of CMOS low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric is demonstrated by the interfacial layer (IL) engineering of HfO2/poly-Si interface. P-channel LTPS-TFT has much higher Idrv ~ 0.789 mA than the n-channel LTPS-TFT ~ 0.274 mA under the same overdrive gate voltage. This asymmetric Idrv is due to the characteristics of field effect mobility μFE that p-channel LTPS-TFT has much higher hole μFE ~ 80.16 cm2/Vs than the electron μFE ~ 38.26 cm2/V s of n-channel LTPS-TFT. The modification of HfO2/poly-Si interface by O2 plasma can enhance the electron μFE ~ 34% and reduce the hole μFE ~ 22.4%, resulting in balanced Idrv of CMOS LTPS-TFTs that n-channel device shows Idrv ~ 0.553 mA and p-channel device shows Idrv ~ 0.590 mA. In addition, the phonon scattering would also be improved by the IL growth and recovered to initial condition after IL removal. Consequently, the IL engineering of CMOS LTPS-TFTs with HfO2 gate dielectric would be a good candidate for the application of system-on-panel or 3-D integrated circuits.

Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors for System-on-Glass

SUMMARY Self-aligned four-terminal (4T) planar metal double-gate (DG) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature (LT), which is below 550 ◦ C, to realize high performance and low power dissipation system-onglass (SoG). The top gate (TG) and bottom gate (BG) were formed from tungsten (W); the BG was embedded in the glass substrate and the TG was fabricated by a self-alignment process using the BG as a photomask. This structure is called embedded metal double-gate (E-MeDG) in this paper. The poly-Si channel with lateral large grains was fabricated using a continuous-wave laser lateral crystallization (CLC). The self-aligned 4T E-MeDG LT poly-Si TFT, with a gate length of 5 m and TG and BG SiO2 thicknesses of 50 and 100nm, respectively, exhibited a subthreshold swing of 120mV/ dec and a threshold voltage (Vth) of 0.5V in the connecting DG mode; i.e. when TG is connected to BG. In the TG operation at various BG control voltage, a threshold voltage modulation factor ( = ∆Vth/∆ VBG) of 0.47 at negative BG control voltage and 0.60 at positive BG control voltage are demonstrated, which values are nearly equal to theoretical prediction of 0.40 and 0.75. Trend of subthreshold swing (s.s.) of TG operation under different BG control voltage are also consistent with theoretical prediction. In addition to TG operation, successful BG operation under various TG control voltages was confirmed. Field-effect mobility derived from gm also varied depending on control gate voltage. The high controllability of device parameter of individual LT poly-Si TFTs is caused by excellent crystalline quality of CLC poly-Si film and will enable us to

Impact of the Hydrogenation Process on the Performance of Self-Aligned Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors

We investigated hydrogenation of low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) from the point of view of the gettering phenomenon, specifically, using self-aligned metal double-gate p-channel LT poly-Si TFTs that had a small subthreshold swing value and a high field-effect mobility. Hydrogenation of TFTs was carried out by forming gas annealing. Our results indicate that the conventionally used hydrogenation temperature of 400 °C is considerably high because annealing at this temperature results in the re-emission of gettered hydrogen. Moreover, when annealing in forming gas, hydrogenation actually occurs during cooling from 400 °C, but not at 400 °C. The most important parameter for effective hydrogenation is the rate of cooling from 400 °C, but not the hydrogenation temperature of 400 °C.

High-Performance Polycrystalline-Silicon Nanowire Thin-Film Transistors With Location-Controlled Grain Boundary via Excimer Laser Crystallization

High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) are demonstrated using excimer laser crystallization to control the locations of grain boundaries two-dimensionally. Via the locally increased thickness of the amorphous-silicon (a-Si) film as the seeds, the cross-shaped grain boundary structures were produced among these thicker a-Si grids. The NW TFTs with one primary grain boundary perpendicular to the channel direction could be therefore fabricated to achieve an excellent field-effect mobility of 346 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s and an on/off current ratio of 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> . Furthermore, the grain-boundary-location-controlled NW TFTs also exhibited better reliability due to the control of grain boundary locations. This technology is thus promising for applications of low-temperature poly-Si TFTs in system-on-panel and 3-D integrated circuits.

A Novel SONOS Memory With Recessed-Channel Poly-Si TFT via Excimer Laser Crystallization

A silicon-oxide-nitride-oxide-silicon memory with recessed-channel (RC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) via excimer laser crystallization (ELC) has been demonstrated to achieve a high mobility of ~ 400 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s and a large ON/OFF current ratio of ~ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> . Such a high performance is because the RC poly-Si TFTs possess only one perpendicular grain boundary (GB) in the channel and the corresponding protrusion at this GB. In addition, the proposed devices also exhibited the largest memory window of 2.63 V in 10 ms with respect to 2.37 and 1.31 V for the conventional-ELC and solid-phase-crystallized ones, respectively. Since the silicon grain growth could be artificially controlled, the device-to-device uniformity could be significantly improved. Therefore, such a simple scheme is promising for applications of low-temperature poly-Si TFTs in 3-D ICs and system on panel.

Oxide Thinning and Structure Scaling Down Effect of Low-Temperature Poly-Si Thin-Film Transistors

In this paper, the gate oxide thickness, and the channel length and width of low-temperature poly-Si thin-film transistors (LTPS-TFTs) have been comprehensively studied. The scaling down of gate oxide thickness from 50 to 20 nm significantly improves the subthreshold swing (S.S.) of LTPS-TFTs from 1.797 V/decade to 0.780 V/decade and the threshold voltage VTH from 10.87 V to 5.00 V. Moreover, the threshold voltage VTH roll-off is also improved with the scaling down of gate oxide thickness due to gate capacitance density enhancement. The channel length scaling down also shows significant subthreshold swing S.S. improvement due to a decreasing of the channel grain boundary trap density Nt. However, the scaling down of channel length also increases the series resistance effect, resulting in the degradation of the field-effect mobility μFE. Therefore, the channel length dependence of field-effect mobility μFE is slightly different with different channel width due to the competition of channel grain boundary trap density effect and series resistance effect.

Novel Two-Bit-per-Cell Resistive-Switching Memory for Low-Cost Embedded Applications

A novel two-bit-per-cell embedded nonvolatile memory (NVM) device requiring no additional mask and process modification in a logic technology has been proposed using a low-temperature poly-Si thin-film transistor with a gate stack. The feature of two-bit-per-cell is realized by independent localized resistive switching (RS) at the drain and source bits, respectively, and enables increased bit density over the present single-poly NVM for low-cost embedded applications. Furthermore, minimal degradation of the transistor characteristics after RS allows interchangeable logic/memory operations in an identical device.