Bias temperature instability comparison of CMOS LTPS-TFTs with HfO2 gate dielectric

Abstract

In this paper, the positive and negative bias temperature instability (P/NBTI) of complementary metal–oxide–semiconductor (CMOS) low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are studied simultaneously. Significant threshold voltage shift ΔVTH, degradation of the subthreshold swing S.S. and transconductance Gm are observed for both n-type LTPS-TFTs after PBTI stress and p-type LTPS-TFTs after NBTI stress. Moreover, the Gm degradation rate with the stress time of p-type devices during NBTI shows significantly different behavior from the PBTI of n-type devices. The PBTI of n-type device shows a saturation behavior of the Gm degradation with various stress bias and temperature. Conversely, the NBTI of p-type device shows an enhanced Gm degradation rate with the increase of stress time and stress temperature. In addition, the threshold voltage shift |ΔVTH| of PBTI does not obey the traditional empirical power law model, but the NBTI obeys it with higher time exponent. Consequently, the NBTI of the p-type device shows worse driving current Idrv degradation than the PBTI of the n-type device mainly due to the different Gm degradation behavior.