Charge-Trap Inactivation of Multi-Line-Beam Clc Poly-Si Tfts Using Channel Impurity Doping

Abstract

Linearly-arranged long silicon crystal grains have been formed by using Multi-Line-Beam Continuous-wave laser Lateral Crystallization (MLB-CLC). Crystallinity of the laser-crystallized poly-Si thin film are biaxially oriented to (110)-(111)-(211) crystal orientation. The low-temperature poly-Si thin film transistors (LTPS-TFTs), however have a high-OFF leakage current and ON/OFF ratio become small. Charge traps on the long grain boundaries between source and drain would induce the high-OFF leakage current. In this work, we introduce a channel doping for inactivation of the traps, and high ON/OFF ratio is achieved. Poly-Si TFTs were fabricated as follows. Buffer SiO2 film (1 μm), a-Si (150 nm) and cap SiO2 (100 nm) were deposited on a quartz substrate. CW laser lateral crystallization with multi-line laser-beam spot was carried out on the a-Si films. The wavelength of the laser was 532 nm, and laser power and scan speed were 7.5 W and 0.5 cm/s, respectively. After the laser crystallization, the cap SiO2 was etched with buffered HF aqueous solution (BHF). In order to pattern the poly-Si active layer, lithography and dry etching (Cl2: 20 sccm, HBr: 20 sccm) were performed. Channel doping on channel region was carried out by boron (B) ions with 3 conditions (ion dose: 5×1012 cm-2, 7×1012 cm-2, 9×1012 cm-2, acceleration voltage: 19 keV). Gate SiO2 (42 nm) was deposited with ICP- CVD. Mo gate electrode (300 nm) was deposited by sputtering method. After resist patterning, the gate electrode was etched with an aqueous solution of H3PO4: HNO3: CH3COOH: H2O = 400: 25: 50: 25. A self-aligned S/D regions were formed by As ion doping (ion dose: 2×1015cm-2, acceleration voltage: 66 keV). Activation anneal was carried out at 550℃ in N2 ambient for 30 minutes. A sacrificial oxide layer in the S/D region was removed with BHF. After the removal, interlayer SiO2 film was deposited with APCVD. Contact holes were formed on the APCVD interlayer dielectric film with BHF. Mo metal pad was deposited by sputtering method, and finally the samples were sintered at 400°C in H2 ambient for 30 minutes. The IDS - VGS characteristic of the fabricated poly-Si TFTs are shown in Fig.1. As the boron impurity concentration increased, the off-leakage current was reduced. It is considered that boron impurity compensated the defect traps in the channel region. At the concentration of 1.3×1020 cm-3, the off leakage current at Vg=0 V was 3×10-11 A and ON/OFF ratio was 106. ON current was reduced by introducing the channel impurity. The electron field-effect mobilities for the boron impurities of 7.1×1019 cm-3, 1.0×1020 cm-3 and1.3×1020 cm-3 were 398, 333, and 261 cm2/Vs, respectively. By introducing boron impurity, the Coulomb scattering was occurred and the electron mobility was reduced. Figure 1