Low-temperature poly-Si Thin-film Transistors Research Articles

A capacitive fingerprint sensor chip using low-temperature poly-Si TFTs on a glass substrate and a novel and unique sensing method

We have developed a capacitive fingerprint sensor chip using low-temperature poly-Si thin film transistors (TFTs). We have obtained good fingerprint images which have sufficient contrast for fingerprint certification. The sensor chip comprises sensor circuits, drive circuits, and a signal processing circuit. The new sensor cell employs only one transistor and one sensor plate within one cell. There is no leakage current to other cells by using a new and unique sensing method. The output of this sensor chip is an analog wave and the designed maximum output level is almost equal to the TFT's threshold voltage, which is 2-3 V for low-temperature poly-Si TFTs. We used a glass substrate and only two metal layers to lower the cost. The size of the trial chip is 30 mm×20 mm×1.2 mm and the sensor area is 19.2 mm×15 mm. The size of the prototype cell is now 60 μm×60 μm at 423 dpi, but it will be easy to increase the resolution up to more than 500 dpi. The drive frequency is now 500 kHz and the power consumption is 1.2 mW with a 5-V supply voltage. This new fingerprint sensor is most suitable for mobile use because the sensor chip is low cost and in a thin package with low power consumption.

Improvement of polycrystalline silicon thin film transistor using oxygen plasma pretreatment before laser crystallization

The device characteristics of the excimer laser recrystallize low temperature poly-Si (polycrystalline silicon) thin-film transistor (TFT) has been improved by employing an oxygen plasma pretreatment on the active amorphous silicon layer prior to the laser crystallization. The oxygen plasma pretreatment has reduced the number of interface traps and increased the field effective mobility in the polysilicon TFT. The device stability of the oxygen plasma pretreated TFTs under the dc stress has been improved due to strong Si-O bond formation during the laser recrystallization.

Fabrication of Low-Temperature Poly-Si Thin Film Transistors with Self-Aligned Graded Lightly Doped Drain Structure

A novel approach for fabricating low-temperature poly-Si (LTPS) thin film transistors (TFTs) with self-aligned graded lightly doped drain (LDD) structure was demonstrated. The self-aligned graded LDD structure was formed by side-etching the Al gate under the photoresist followed by excimer laser irradiation for dopant activation and lateral diffusion. The graded LDD poly-Si TFTs exhibited low-leakage-current characteristics without significantly sacrificing driving capability due to the graded dopant distribution in the LDD regions, in which the drain electric field could be reduced. The leakage current of 1 μm graded LDD LTPS TFTs at Vds = 5 V and Vgs = -10 V could reach below 1 pA/μm, and the on/off current ratio at Vds = 5 V exceeded 10 7 .

Analysis of Hot Carrier Effect in Low-Temperature Poly-Si Thin-Film Transistors towards High Reliability

Analysis of Hot Carrier Effect in Low-Temperature Poly-Si Thin-Film Transistors towards High Reliability

High-performance low-temperature poly-Si TFTs crystallized by excimer laser irradiation with recessed-channel structure

High-performance low-temperature poly-Si (LTPS) thin-film transistors (TFTs) have been fabricated by excimer laser crystallization (ELC) with a recessed-channel (RC) structure. The TFTs made by this method possessed large longitudinal grains in the channel regions, therefore, they exhibited better electrical characteristics as compared with the conventional ones. An average field-effect mobility above 300 cm/sup 2//V-s and on/off current ratio higher than 10/sup 9/ were achieved in these RC-structure devices. In addition, since grain growth could be artificially controlled by this method, the device electrical characteristics were less sensitive to laser energy density variation, and therefore the uniformity of device performance could be improved.

A novel two-step laser crystallization technique for low-temperature poly-Si TFTs

We present investigations on a novel technique for preparing low-temperature poly-Si thin-film on glass substrates using two-step laser crystallization. In the first step, seeds are created by excimer laser induced crystallization of very thin (26 nm) amorphous silicon (a-Si) thin-films deposited by plasma enhanced chemical vapor deposition (PECVD). A second (a-Si) thin-film of 80-120 nm is used to obtain large crystalline grains grown around the seed crystallites during the second laser crystallization. Using this two-step crystallization (TSC) approach, we fabricated poly-Si thin-film transistors (TFTs) with electron mobility of 103 cm/sup 2//V/spl middot/s and ON/OFF current ratio of 10/sup 7/. They are two times and four times higher than those of the poly-Si TFTs fabricated in the same run using conventional single-step excimer laser crystallization.

Low-Temperature Polycrystalline Silicon Thin-Film Transistors for Large-Area Liquid Crystal Display

A low-temperature poly-Si thin-film transistor (TFT), having inverted-staggered structure, has been developed successfully using excimer laser annealing and ion doping. This TFT is suitable for pixel transistors of large-area and high-resolution LCDs. The maximum process temperature of the TFT fabrication steps is less than 450°C, so the same glass substrate on which amorphous Si TFT arrays are formed can be used in this poly-Si TFT process. Furthermore, most of the procedures, equipment and thin-film materials used to fabricate amorphous Si TFTs are compatible with fabrication of the poly-Si TFTs. On the other hand, some investigation of the CMOS driver circuit has been done, and it has been found that the threshold voltage of these poly-Si TFTs can be controlled easily by lightly doping of B ion into the channel region using the ion doping system.

Fabrication of a poly-Si thin-film transistor with storage capacitor

The fabrication process of a low-temperature poly-Si thin-film transistor (TFT) with a storage capacitor was studied. The atmospheric-pressure chemical-vapour deposited SiO 2 protected the buried indium tin oxide (ITO) from reduction by a pure H 2 plasma treatment that was essential for the effective improvement of the poly-Si TFT characteristics. Thus, a storage capacitor with an ITO (picture electrode)-SiO 2-ITO (buried common electrode) structure was successfully fabricated. The poly-Si TFT with a channel width/length W L ratio of 5 drove a 3 pF storage capacitor in 2 μs, and it showed superior driverability for LCD use. The TFT also had good hold characteristics under illumination for the realization of grey-scale representation.