Low Switching Speed Research Articles

The Sustained Oscillation Modeling and Its Quantitative Suppression Methodology for GaN Devices

Gallium nitride (GaN) devices are widely used due to their excellent performance when integrated into power electronics applications. However, owing to their low parasitic parameters and fast switching speed, they are more prone to instability than the silicon devices. The sustained oscillation discussed in this article is one of the instability problems, which may result in overshoot or even more serious device breakdown; thus, it is pretty necessary to suppress it effectively in practical applications. It is the first time to adopt an RC snubber to suppress the sustained oscillation in this article, which is very simple and cheap but effective. First, the sustained oscillation modeling based on a double pulse circuit is carried out. Then, the RC region is established quantitatively according to the root locus analysis results, which makes up for the defects of these qualitative methods before. Furthermore, it is first found that the sustained oscillation can be fully suppressed due to the existence of dipoles. Finally, the oscillation suppression effect within the RC region is compared with that outside the region by the simulation and experimental results, which are consistent with the theoretical analysis. Additionally, the possible negative influence of the added RC snubber is also discussed in this article, which shows that it has a little impact on the switching speed and energy loss, while the sustained oscillation is well suppressed.

Implementation and Comparative Analysis of Low Power Multiplexers Using Dynamic Logic Styles

This paper presents the implementation and comparative analysis of low power multiplexers using dynamic logic styles. A multiplexer is a digital circuit with 2N input lines with N selection lines and gives a single output. Dynamic logic styles were used in conventional CMOS for optimizing power, area, and delay, etc. Different types of dynamic logic styles such as complementary CMOS, pseudo NMOS, domino differential cascade voltage switch logic, low power feed through logic, and clocked CMOS logic were used for the implementation of a multiplexer. In this present work, the implementation of 2:1 multiplexer using different dynamic logic styles with various technologies (120nm, 90nm, 70nm) and the performance parameters such as power consumption and delay were compared and analyzed. The clocked CMOS was found efficient in low power consumption and fast switching speed. Among the different logic styles, Domino, clocked and low power feed through logic produces efficient in delay and power consumption. The implementation and simulation of low power multiplexers were carried out by using DSCH 2.6F microwind tool.

A Review of Switching Oscillations of Wide Bandgap Semiconductor Devices

Wide bandgap (WBG) devices offer the advantages of high frequency, high efficiency, and high power density to power converters due to their excellent performance. However, their low parasitic capacitance and fast switching speed also make them more susceptible to switching oscillations. The switching oscillations can cause voltage and current overshoots, shoot-through, electromagnetic interference, additional power loss, and even device damage, which can seriously affect the performance of power converters and systems. However, a comprehensive and in-depth overview is lacking on this topic. This article reviews the types, the causes and negative effects, the effects of parasitic parameters and suppression methods of these switching oscillations, which is helpful for practical engineering. First, the switching oscillations are divided into different types, and their causes and negative effects are reviewed. Then, the effects of different parasitic parameters on the switching oscillations are overviewed. It is found that due to the different physical structures of silicon carbide metal-oxide-semiconductor field-effect transistors, enhancement-mode gallium nitride high-electron mobility transistors (eGaN HEMTs), and cascode GaN HEMTs, the effects are also different. Finally, the main methods of suppressing the switching oscillations are summarized, and the advantages and disadvantages of these methods are presented. Furthermore, future research works on this topic and the conclusion of this paper are drawn, which will help readers deepen their understanding of the switching oscillations of WBG devices, and inspire readers to better use WBG devices for high-frequency and high-efficient power conversion.

Optimized DL-TFET Design for Enhancing its Performance Parameters by Using Different Engineering Methods

ABSTRACT Dopingless Tunnel Field Effect Transistor is a prominent device because of its low sub-threshold swing and fast switching speed. In this paper, DL-TFET is investigated for enhancing the performance parameters by applying different engineering techniques. The hetero-junction is implemented in the DL-TFET for increasing the ION current. Further, for reducing the ambipolar current and enhancing the ON-characteristics by introducing the non-uniform oxide layer, hetero-gate and then further optimization is done by varying the “x” compositions of In1-xGaxAs for source side material. The various staggered hetero-gate hetero-junction DL-TFET structures with different EBeff are comparatively investigated for analyzing their performance parameters. Among them, highly staggered Hetero-junction DL-TFET with EBeff = 0.374 eV shows better performance as lower threshold voltage, higher ION current, high transconductance and lower sub-threshold swing. So, the In0.45Ga0.55As/In0.25Ga0.75As based hetero-gate at TG = 4.2 eV and Θ = 7.59° heterojunction DL-TFET structure can be chosen for fast switching and advanced circuit application.

A Step Towards Optimisation of 2 to 4 Decoder Using Farooq-Nikesh-Zaid Gate with Coplanar Crossing in Quantum Dot Cellular Automata

The limitations of the existing Complementary Metal Oxide Semiconductor are leading the momentum to various new approaches like Quantum-dot Cellular Automata (QCA). QCA offers low power dissipation, less area and high switching speeds. The Majority Voter is the basic structure that votes out on the majority of the inputs to implement a Boolean Function. The QCA architectures are created by using majority gates with inverters or by using universal gates like AND–OR-Inverter and NAND–NOR-Inverter gate. This paper proposes a quantum-dot cellular automata 2 to 4 decoder using Universal Farooq-Nikesh-Zaid gate, which utilizes the NAND gate logic to implement the functionality. The design offers 33% reduction in the cell count, reduction in the area with Six Clock Phases in simple co planar wire crossing. The proposed design is validated using the QCA Designer tool.

Phase Change Materials for Nonvolatile, Solid‐State Reflective Displays: From New Structural Design Rules to Enhanced Color‐Changing Performance

AbstractWith the arrival of omnimedia era, there has been an increasing demand for energy‐saving, colorful, and portable displays. Traditional display technologies, such as electrophoresis and electronic ink display suffer from low color switching speed and poor color richness. Due to their high performances, phase change materials (PCMs)‐based nonvolatile, solid‐state reflective display coatings have become the most promising materials for new portable display technology. Existing researches mainly focus on improving the color‐changing performance of coatings by optimizing film structural parameters, but ignore improving the performance by designing new PCMs. Here, this study reveals the color‐changing mechanisms of display coatings through a combination of experiments, first‐principles calculations, spectral fitting, and optical simulation. It is found that reducing the vacancy concentrations of PCMs can increase the color‐changing performance of coatings owing to the increase in p–p coupling strength. Based on previous reports and the new insights into p–p coupling strength, this study proposes three structural design principles of ideal PCMs (low ionicity, a limited degree of hybridization, and high p–p coupling strength) and predicts new PCM candidates for display applications. This study opens a broad avenue for developing nonvolatile display technologies and material selection.

Low power-high speed performance of 8T static RAM cell within GaN TFET, FinFET, and GNRFET technologies – A review

Recent ULSI technology development emphasizes both silicon and graphene-based devices and system performance in terms of their low power and high switching speed. With Moore’s law scaling having reached the limits of physics due to ballistic effects, efforts are moving towards nano scale materials and devices such as TFETs and GNRFETs. Still, recent developments with 7 nm lithography-based silicon devices have cited exciting results. The successful development of FinFET devices in integrated systems has been a breakthrough for the semiconductor industry. Research efforts were emphasized for new nanoscale materials such as Graphene, GaN, and Carbon nanotubes, as alternative devices for ULSI integrated system design. This paper provides a cumulative review for these three nanoscale devices: FinFET, TFET, and GNRFET. The study focuses on an 8T SRAM cell as geared towards low power and high-speed features that are suitable for high speed computers, wireless communications, and medical devices. The study covers device theory, models, and simulation. The study has showed evidence that the power consumption for both TFET and GNRFET -based systems features superior low power performance of a ratio 1:0.24 as taken for the Static T Cell for 20 nm scale devices. The practical model of the FinFET is verified and used by industry, while the practical model of both TFET and GNRFET are still in the prototype stage.

A novel locomotive auxiliary converter control strategy with harmonic suppression for avoiding resonance voltage accidents in an electrified railway

In recent years, the AC‐DC‐AC electric locomotives have been wildly applied in electrified railways, deteriorating the current quality of network. Therefore, filters in electrified railways are essential. However, considering the volume and weight of filters, it is inappropriate to install them on locomotives. And resonance accident caused by high‐frequency harmonics is hard to suppress because of the low switching speed of high‐power Si‐based devices. In this article, a novel locomotive auxiliary converter control strategy with harmonic suppression function is proposed to filter harmonic currents injected into the traction supply network. By controlling the auxiliary converter, the strategy could complete the function of rectification and filtering, converting power for auxiliary equipment, filtering the harmonic current, and suppressing resonance accidents with the high‐frequency characteristics of SiC devices. For compensating high‐frequency harmonics, the parameters of main circuit and control scheme are analyzed to ensure a stable system. The feasibility of the scheme is verified by simulation and RT‐LAB hardware‐in‐loop experiment. © 2019 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Low power device design application by magnetic tunnel junctions in Magnetoresistive Random Access Memory (MRAM)

The spintronics techniques combines the spin degree and charge which gives rise to state of the art devices like magnetic tunnel junctions which are ultra-low power devices. It is proposed in the paper to evaluate magnetic tunnel junctions (MTJ) at the device level. The paper present an overview of fabrication process, while considering different aspects of the characteristics of MTJs, performance, challenges and a wide range of applications which are different from conventional CMOS technology. The MTJ devices are CMOS compatible for non-volatility, high stability and reliability. The MTJ device is a promising candidate for building non-volatile circuits for ultra- low power operation and fast switching speeds. The current approaches to design logic functionalities and memory devices with MTJs w include hybrid CMOS and MTJ circuits are also discussed in the paper. The results on the most robust magnetic tunnel junction with Resistance Area = 8 Ω-µm2 demonstrates that it satisfies the statistical requirements in parallel with high magnetic tunnel resistance greater than 15σ(Rp), breakdown-of voltage to edge more than 0.5 V, read-induced rate beneath 10−9, and with adequate write endurance, free of undesirable write endurance magnetic inversion. Also this paper demonstrates on the most vigorous MTJ with Resistance Area = 8 Ω-µm2 that satisfies the statistical requirements in parallel with high magnetic tunnel resistance greater than 15σ(Rp),breakdown-of voltage to edge more than 0.5 V, read-induced rate less than 10−9, and with adequate write endurance, and is free of undesirable write endurance magnetic inversion.

3D Stackable and Scalable Binary Ovonic Threshold Switch Devices with Excellent Thermal Stability and Low Leakage Current for High‐Density Cross‐Point Memory Applications

AbstractThe development of selector devices is essential for the implementation of dense memory arrays. Ovonic threshold switch (OTS) devices have gained interest as high‐performance selectors, but their material complexity and low thermal stability remain concerns. The effect of element compositions and its types on binary telluride‐based OTS are investigated to develop selectors that meet the simple material composition and high thermal stability requirements while ensuring low OFF‐state leakage current (IOFF). Through a careful control of Te composition in binary tellurides, binary OTS devices with low IOFF (≈5 nA) and fast switching speed (<10 ns) are obtained. In addition, high endurance (108) and thermal stability (450 °C) are achieved by adopting tellurides including small elements. The high thermal stability of the developed OTS devices results from the strong covalent bonds between Te and small elements that prevent crystallization of the tellurides, which is revealed by performing first‐principles calculations. The binary OTS are also compatible with a 3D stacking technology, which is confirmed by fabricating a 3D B‐Te‐based device that shows good OTS characteristics. In addition, the OTS device successfully suppresses the leakage current in half‐selected cells when it is integrated with a resistive random access memory (ReRAM) device.

Hybrid bilayer gate dielectric-based organic thin film transistors

Organic thin film transistors (OTFTs) are key building blocks for flexible, low cost electronics systems. They provide a viable alternative for silicon-based electronics with added advantages of low cost and flexibility. However, few issues like high-operating voltage, low-switching speed, high-leakage current and reliability are still a challenge. The overall performance of an OTFT depends on organic semiconductors and gate dielectric interface. In this paper, we review the current status and trends in the choice of dielectric layer for OTFTs. As a starting point, the performance parameters of an OTFT and their dependence on the dielectric layer are briefly discussed. A variety of dielectric materials which includes high-k inorganic, organic, surface coated inorganics and nanocomposites are also presented. The advantages and drawbacks of each of these materials are discussed in detail. We reviewed the latest developments in the dielectric materials especially, self-assembled monolayers (SAMs), hybrid bilayers and nanocomposites. SAM-based OTFTs offer several advantages but shift in the threshold voltage remains a concern. Nanocomposites are a latest addition to the dielectric materials, which offer advantages like solution processing and improved dielectric constant but have a rough surface. A hybrid bilayer that incorporates the inorganic dielectric as a base layer and a thin polymer layer over it to improve the surface properties offers several desirable characteristics over the other choices. Hence, we propose that hybrid bilayer gate dielectrics shall play a pivotal role in improving the OTFT performance.

Inkjet-printed co-continuous mesoporous oxides for high-current power transistors.

Limited printing resolution has always been a major hindrance for printed electronics; irrespective of the high mobility demonstrated by solution-processed semiconductors, long-channel printed field-effect transistors (FETs) have demonstrated low On-state conductance and switching speeds. Although various concepts have been proposed to obtain narrow-channel printed FETs, the actual demonstration of high On-currents/channel conductance has been rare. In this context, herein, we report a general recipe to print co-continuous mesoporous structures with high surface-to-volume ratios for the first time for a large range of metallic and semiconducting oxides, both n- and p-type; next, by exploiting an innovative transistor architecture by printing an additional silver layer on top of the printed porous channel, we reduced the necessary length of electronic transport through the semiconductor material to a short vertical distance of the order of a few tens of nanometres. Basically, when a composite solid polymer electrolyte was used as a gate insulator, we essentially obtained channel length-independent transport with the unprecedented On-current of 67 μA μm-1 and transconductance of 143 μS μm-1 at the supply voltage of only 0.5 V. Among others, one may foresee the usage of these devices in high power switches and for drawing power from batteries in all-printed electronic circuits.

Stress induced modulation of magnetic domain diffraction of single crystalline yttrium iron garnet

Stress induced modulation of the diffraction angle and efficiency of the light reflected from a stripe-domain magnetic garnet was demonstrated. The spacing of the magnetic domain was changed using the inverse magnetostriction effect. The sample structure was a piezo actuator/Al reflection layer/magnetic garnet substrate. A diffraction angle between the 0th and 1st ordered light was changed from 9.12 deg. to 10.20 deg. This result indicates that the domain spacing was changed from 3.3 μm to 3.0 μm. The change of the diffraction angle was irreversible for the voltage. However, reversible, linear and continuous change of the diffraction efficiency was observed. These results could be applicable for a voltage-driven optical solid state light deflector with low power consumption and high switching speed.

Possible Models of Electron-Energy Transfer in Resistance Switching by Sputter-Deposited Silicon Oxide Films: Potential of Extremely Low-Energy Switching

This paper uses various experimental results to discuss possible chemical processes in the resistance switching of sputter-deposited silicon oxide films. It is clearly demonstrated that the power dissipated during the transition from the low resistance state to high resistance state is sensitive to the compliance current level at the initial forming. Aspects of the low resistance state to high resistance state transition are categorized by the power law of the compliance current level, suggesting likely physics associated with the switching process. Regarding the low resistance state to high resistance state transition, the critical transition energy for resistance switching suggests the feasibility of very low-switching-energy density (∼10−15 J/μm2) albeit with low switching speed; images of the chemical bonds in the low resistance state and the high resistance state are proposed based on the measured results. It is strongly suggested that while E’ centers assist resistance switching from the high resistance state to the low resistance state, oxygen vacancy creation dominates this switching process.

An Analytical Model for False Turn-On Evaluation of High-Voltage Enhancement-Mode GaN Transistor in Bridge-Leg Configuration

Compared with the state-of-the-art Si-based power devices, enhancement-mode Gallium Nitride (E-mode GaN) transistors have better figures of merit and exhibit great potential in enabling higher switching frequency, higher efficiency, and higher power density for power converters. The bridge-leg configuration circuit, consisting of a controlling switch and a synchronous switch, is a critical component in many power converters. However, owing to the low threshold voltage and fast switching speed, E-mode GaN devices are more prone to false turn-on phenomenon in bridge-leg configuration, leading to undesirable results, such as higher switching loss, circuit oscillation, and shoot through. In order to expand gate terminal's safe operating margin without increasing reverse conduction loss during deadtime, negative gate voltage bias for turn-off and antiparallel diode could be applied to E-mode GaN device. In this paper, with consideration of strong nonlinearities in C–V and I–V characteristics of high-voltage (650 V) E-mode GaN transistors, analytical device models are first developed. Then, we develop an analytical circuit model that combines the circuit parameters with intrinsic characteristics of the high-voltage GaN transistor and antiparallel diode. Thus, key transient waveforms with regard to the false turn-on problem can be acquired, including displacement current and false triggering voltage pulse on gate terminal. The simulated waveforms are then verified on a testing board with GaN-based bridge-leg circuit. In contrast to piecewise switching process models and PSpice simulation, the proposed model exhibits outstanding performances. To provide design guidelines for mitigating false turn-on of GaN transistor, the impacts of different circuit parameters, along with the optimum negative gate voltage bias, are investigated based on the proposed model.

Resistive Switching Performance Improvement via Modulating Nanoscale Conductive Filament, Involving the Application of Two-Dimensional Layered Materials.

Reversible chemical and structural changes induced by ionic motion and reaction in response to electrical stimuli leads to resistive switching effects in metal-insulator-metal structures. Filamentary switching based on the formation and rupture of nanoscale conductive filament has been applied in non-volatile memory and volatile selector devices with low power consumption and fast switching speeds. Before the mass production of resistive switching devices, great efforts are still required to enable stable and reliable switching performances. The conductive filament, a bridge of microscopic metal-insulator-metal structure and macroscopic resistance states, plays an irreplaceable part in resistive switching behavior, as unreliable performance often originates from unstable filament behavior. In this Review, departing from the filamentary switching mechanism and the existing issues, recent advances of the switching performance improvement through the conductive filament modulation are discussed, in the sequence of material modulation, device structure design and switching operation scheme optimization. In particular, two-dimensional (2D) nanomaterials with excellent properties including and beyond graphene, are discussed with emphasis on performance improvement by their active roles as the switching layer, insertion layer, thin electrode, patterned electrode, and edge electrode, etc.

Analysis of Parasitic Elements of SiC Power Modules With Special Emphasis on Reliability Issues

Commercially available silicon carbide (SiC) MOSFET power modules often have a design based on existing packages previously used for silicon insulated-gate bipolar transistors. However, these packages are not optimized to take advantage of the SiC benefits, such as high switching speeds and high-temperature operation. The package of a half-bridge SiC MOSFET module has been modeled and the parasitic elements have been extracted. The model is validated through experiments. An analysis of the impact of these parasitic elements on the gate-source voltage on the chip has been performed for both low switching speeds and high switching speeds. These results reveal potential reliability issues for the gate oxide if higher switching speeds are targeted.

Low Actuating Voltage Spring-Free RF MEMS SPDT Switch

RF MEMS devices are known to be superior to their solid state counterparts in terms of power consumption and electromagnetic response. Major limitations of MEMS devices are their low switching speed, high actuation voltage, larger size, and reliability. In the present paper, a see-saw single pole double throw (SPDT) RF MEMS switch based on anchor-free mechanism is proposed which eliminates the above-mentioned disadvantages. The proposed switch has a switching time of 394 nsec with actuation voltage of 5 V. Size of the SPDT switch is reduced by utilizing a single series capacitive switch compared to conventional switches with capacitive and series combinations. Reliability of the switch is improved by adding floating metal and reducing stiction between the actuating bridge and transmission line. Insertion loss and isolation are better than −0.6 dB and −20 dB, respectively, for 1 GHz to 20 GHz applications.

A Physics-based Memristor Model Based on Chalcogenide Alloy

Memristor, as the fourth fundamental circuit element, has recently attracted considerable attention due to its widespread applications from programmable logic to neural networks. Today, the most representative memristor consists of a thin film of titanium oxide sandwiched by two electrodes. However, such a memristor gives rise to a relatively low switching speed, discouraging it from receiving more research enthusiasm. To overcome the disadvantages of the already established memristors (e.g. low switching speed and poor endurance) and thus to optimize the memristor performance, we proposed a novel memristor concept using chalcogenide alloy that has been widely used for nonvolatile memory storage. According to the developed electro-thermal model, the designed memristor using chalcogenide alloy clearly shows a variation of resistance along with the history of current as well as a fast switching speed and ultra-low energy consumption. Keywords: Cycle, chalcogenide, Ge2Sb2Te5, memristor, model.

Comparative Study of Perforated RF MEMS Switch

Abstract MEMS are the Micro Electronic mechanical system or in general terms it is also known as Micro electronic mechanical switch. MEMS have classified in two types of switch that is series switch and shunt switch .The cantilever is a series type switch whereas the fixed- fixed beam is shunt type switch. Fixed- Fixed beam is the element that is fixed at both anchor ends. The electrostatic actuation process occurs on the switch due to which switch deflects from its original position. The stiction problem occurs in MEMS switches which have been reduced by the proposed design. The perforation is used to reduce the squeeze film damping by decreasing the mass of the switch. As the voltage increases the switch moves to downward z-direction .The displacement is produced in the switch as direction of movement is towards negative z-axis. When the beam contacts with electrode, pull in voltage is achieved. This paper explores the perforation and meander concept with Fixed -fixed switch, which increases the flexibility, low actuation voltage and switching speed. The various types of perforations provide discrete displacement corresponding to voltage. In this paper we represent the design and simulation of Fixed-Fixed switch using perforation of size 2 μm-5 μm. The electrostatic actuation mechanism is applied on the Fixed-fixed switch which has a serpentine meanders and perforation at different voltages. The switch is designed and simulated by using COMSOL®MULTIPHYSICS 4.3b software.