Implementation and Comparative Analysis of Low Power Multiplexers Using Dynamic Logic Styles

Abstract

This paper presents the implementation and comparative analysis of low power multiplexers using dynamic logic styles. A multiplexer is a digital circuit with 2N input lines with N selection lines and gives a single output. Dynamic logic styles were used in conventional CMOS for optimizing power, area, and delay, etc. Different types of dynamic logic styles such as complementary CMOS, pseudo NMOS, domino differential cascade voltage switch logic, low power feed through logic, and clocked CMOS logic were used for the implementation of a multiplexer. In this present work, the implementation of 2:1 multiplexer using different dynamic logic styles with various technologies (120nm, 90nm, 70nm) and the performance parameters such as power consumption and delay were compared and analyzed. The clocked CMOS was found efficient in low power consumption and fast switching speed. Among the different logic styles, Domino, clocked and low power feed through logic produces efficient in delay and power consumption. The implementation and simulation of low power multiplexers were carried out by using DSCH 2.6F microwind tool.