Low-power Circuit Design Research Articles

An efficient circuit-level power reduction technique for ultralow power applications

This research work explores various circuit-level design techniques to identify the best technique suitable for low power circuit design. To establish a proper performance comparison, reported techniques are implemented in a transmission gate-based carry skip adder circuit @ 22-nm technology node. Results obtained demonstrate that the multi-threshold CMOS technique offers the best performance under the given conditions. Further, a novel modified hybrid circuit design technique is also proposed in this paper. To validate the proposed design technique, performance metrics of the carry-skip adder circuit implemented using the proposed hybrid technique and other low power circuit design techniques are compared. Obtained results establish that the proposed technique offers improvement in terms of propagation delay (TP), average power dissipation (PAVG), power delay product (PDP) and leakage power (LP), when compared with its counterpart at a supply voltage of 0.4 V.

A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis

This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of ECG signal acquisition systems. The AFE was realized with a three-stage fully differential AC-coupled amplifier, and it provides bio-signal acquisition with programmable gain and bandwidth. The AFE was implemented in a 130 nm CMOS process, and it has a measured tunable mid-band gain from 31 to 52 dB with tunable low-pass and high-pass corner frequencies. Under only 0.5 V supply voltage, it consumes 68 nW of power with an input-referred noise of 2.8 µVrms and a power efficiency factor (PEF) of 3.9, which makes it very suitable for energy-harvesting applications. The low-noise 68nW AFE was also integrated on a self-powered physiological monitoring System on Chip (SoC) that is used to capture ECG bio-signals. Heart rate extraction (R-R) detection algorithms were implemented and utilized to analyze the ECG data received by the AFE, showing the feasibility of <100 nW AFE for continuous ECG monitoring applications.

A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits

Low power circuit design has been one of the major growing concerns in integrated circuit technology. Reversible circuit (RC) design is a promising future domain in computing which provides the benefit of less computational power. With the increase in the number of gates and input variables, the circuits become complex and the need for fault testing becomes crucial in ensuring high reliability of their operation. Various fault detection methods based on exhaustive test vector search approaches have been proposed in the literature. With increase in circuit complexity, a faster test generation method for providing optimal coverage becomes desirable. In this paper, a genetic algorithm-based heuristic test set generation method for fault detection in RCs is proposed which avoids the need for an exhaustive search. Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.

Design of low-power 2FSK demodulation circuit

Aiming at the complex structure and high power consumption of the existing 2FSK demodulation circuit, this paper designs a simple structure and low power 2FSK demodulation circuit. A CMOS transistor matrix circuit is used to demodulate the 2FSK signals of 1200HZ and 2200HZ. The function model is established by using Matlab, and the number of sampling points is determined according to the simulation results and design requirements, and then the size of CMOS transistor matrix circuit is determined. The circuit uses Cadence software for functional verification, and HSPICE software is used for power consumption analysis. The simulation results meet the design requirements of low power consumption and achieve the desired demodulation effect.

Autonomous Wideband Piezoelectric Energy Harvesting Utilizing a Resonant Inverter

Piezoelectric energy harvesters generate electrical power from ambient mechanical vibrations, making these vibrations a viable energy source for powering wireless sensor and identifier nodes. In order to harvest an appreciable amount of power, piezoelectric devices are typically inserted into high-Q mechanical resonant structures that significantly limit their harvesting bandwidth. The dynamic active energy harvesting method has been proposed as a way to widen the bandwidth of resonant piezoelectric energy harvesters; however, an autonomous design has not yet been demonstrated. This paper demonstrates the first autonomous implementation of this method. This was accomplished through the use of a resonant inverter topology in combination with a low-power analog control circuit design that reduces the computational demand of the microcontroller. Experimental results using the Mide Volture V20w piezoelectric device show that the harvested power is up to twice that of the adaptive rectifier method. These results include previously ignored loss mechanisms such as control losses, gating losses, and phase detection losses, making this system the first autonomous energy harvesting system of its kind.

Energy and Delay Tradeoffs of Soft-Error Masking for 16-nm FinFET Logic Paths: Survey and Impact of Process Variation in the Near-Threshold Region

A near-threshold voltage (NTV) operation provides a recognized approach to low-power circuit design due to its balancing of minor performance degradation relative to its significant power savings. However, the scaling voltage and the technology process give rise to increased susceptibility to radiation-induced soft errors for systems operating at NTV. In this brief, we develop new results for the evaluation of alternatives to mask single-event transients in combinational logic and single-event upsets in storage elements for three commonly utilized redundancy approaches, namely, spatial, temporal, and a hybrid of both spatial and temporal. The performance and energy impact of each approach is quantified at the NTV operation. Additionally, the impact of an increased effect of threshold voltage variation at NTV is assessed for all redundant systems. We also investigate the effect of technology scaling by comparing the energy and performance variation of the 45-nm MOSFET planar and the 16-nm high- $\kappa/$ metal-gate bulk fin-typed field-effect transistor structures as modeled by the Predictive Technology Model NanGate open source library via simulations in HSPICE. The results indicate that delay variation of temporal redundancy (22.34%) is lower than the variation of both triple module redundancy and self-voting dual module redundancy (31.6% and 35.2%, respectively), although the variation of 16-nm is beneath that of 45-nm technology node for both. On average, operating at NTV using trigate 16-nm bulk FinFET devices reduces energy consumption and incurs less performance impact for redundant systems. Utilizing temporal redundancy based on a trigate 16-nm process achieves 56.2% energy savings at a 27.6% delay increase compared with a spatial redundancy approach.

Low-Power High Speed 1-bit Full Adder Circuit Design in DSM Technology

Low-Power High Speed 1-bit Full Adder Circuit Design in DSM Technology

Design Of Low Power And Area Efficient SRAM Architecture Based on GDI Technique

Semiconductor memories are most important subsystem of modern digital systems. In new era the scaling of silicon technology has been ongoing, due to scaling large memory can be fabricated on a single chip as results memories are capable to store and retrieve large amount of information at high speed. But due to high density, power dissipation gets increases and speed decreases. So there is need for the design of low power and high speed circuit in memory. Here presents a new five transistor (5T) CMOS and Fin FET SRAM cell to accomplish improvements in stability, power dissipation, and performance over previous designs, for high speed and high stability memory operation. 5T SRAM using low power reduction techniques. All the simulations have been carried out at Tanner EDA tool. In this project, will modify 5T SRAM cell with the use of high threshold PMOS Devices that results in decrease in the leakage that reduces power dissipation. The circuit designing and simulation is done on the Tanner tool, Schematic of the SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed through the W-edit.

Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique**Project supported by the National Natural Science Foundation of China (No. 61306040), the State Key Development Program for Basic Research of China (No. 2015CB057201), the Beijing Natural Science Foundation (No. 4152020), and Natural Science Foundation of Guangdong Province, China (No. 2015A030313147).

With shrinking transistor feature size, the fin-type field-effect transistor (FinFET) has become the most promising option in low-power circuit design due to its superior capability to suppress leakage. To support the VLSI digital system flow based on logic synthesis, we have designed an optimized high-performance low-power FinFET standard cell library based on employing the mixed FBB/RBB technique in the existing stacked structure of each cell. This paper presents the reliability evaluation of the optimized cells under process and operating environment variations based on Monte Carlo analysis. The variations are modelled with Gaussian distribution of the device parameters and 10000 sweeps are conducted in the simulation to obtain the statistical properties of the worst-case delay and input-dependent leakage for each cell. For comparison, a set of non-optimal cells that adopt the same topology without employing the mixed biasing technique is also generated. Experimental results show that the optimized cells achieve standard deviation reduction of 39.1% and 30.7% at most in worst-case delay and input-dependent leakage respectively while the normalized deviation shrinking in worst-case delay and input-dependent leakage can be up to 98.37% and 24.13%, respectively, which demonstrates that our optimized cells are less sensitive to variability and exhibit more reliability.

Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation.

Implementation of floating gate MOSFET in inverter for threshold voltage tunability

This paper presents the ability of floating gate MOSFET (FGMOS) threshold voltage to be programmed or tuned which is exploited to improve the performance of electronic circuit design. This special characteristic owns by FGMOS is definitely contributes towards low voltage and low power circuit design. The comparison of threshold voltage between FGMOS and conventional NMOS is done in order to prove that FGMOS is able to produce a lower threshold voltage compared to conventional NMOS. In addition, in this paper, an implementation of FGMOS into inverter circuit is also done to show the programmability of FGMOS threshold voltage. The operations of the inverter circuits are verified using Sypnopsys simulation in 0.1μm CMOS technology with supply voltage of 1.8V.

Nanoscale MOSFET Modeling: Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits

This article presents the s implified charge-based Enz-Krummenacher-Vittoz (EKV) [11] metal-oxide-semiconductor field-effect transistor (MOSFET) model and shows that it can be used for advanced complementary metal-oxide-semiconductor (CMOS) processes despite its very few parameters. The concept of an inversion coefficient (IC) is first introduced as an essential design parameter that replaces the overdrive voltage VG-VT0 and spans the entire range of operating points from weak via moderate to strong inversion (SI), including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40- and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation, valid from weak to SI and requiring only the VS parameter mc, is described. The normalized transconductance efficiency Gm/ID, which is a key figure-of-merit (FoM) for the design of low-power analog circuits, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to SI with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance Gds/ID follows a similar dependence with IC than the normalized Gm/ID characteristic but with different parameters accounting for drain induced barrier lowering (DIBL). The methodology for extracting the few parameters from the measured ID-VG and ID-VD characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted silicon on insulator (FDSOI) and Fin-FET 28-nm processes.

EC-CENTRIC: An Energy- and Context-Centric Perspective on IoT Systems and Protocol Design

The radio transceiver of an Internet of Things (IoT) device is often where most of the energy is consumed. For this reason, most research so far has focused on low-power circuit and energy-efficient physical layer designs, with the goal of reducing the average energy per information bit required for communication. While these efforts are valuable per se, their actual effectiveness can be partially neutralized by ill-designed network, processing, and resource management solutions, which can become a primary factor of performance degradation, in terms of throughput, responsiveness, and energy efficiency. The objective of this paper is to describe an energy-centric and context-aware optimization framework that accounts for the energy impact of the fundamental functionalities of an IoT system and that proceeds along three main technical thrusts: 1) balancing signal-dependent processing techniques (compression and feature extraction) and communication tasks; 2) jointly designing channel access and routing protocols to maximize the network lifetime; and 3) providing self-adaptability to different operating conditions through the adoption of suitable learning architectures and of flexible/reconfigurable algorithms and protocols. After discussing this framework, we present some preliminary results that validate the effectiveness of our proposed line of action, and show how the use of adaptive signal processing and channel access techniques allows an IoT network to dynamically tune lifetime for signal distortion, according to the requirements dictated by the application.

Active Electrodes for Wearable EEG Acquisition: Review and Electronics Design Methodology.

Active electrodes (AEs), i.e., electrodes with built-in readout circuitry, are increasingly being implemented in wearable healthcare and lifestyle applications due to AEs' robustness to environmental interference. An AE locally amplifies and buffers μV-level EEG signals before driving any cabling. The low output impedance of an AE mitigates cable motion artifacts, thus enabling the use of high-impedance dry electrodes for greater user comfort. However, developing a wearable EEG system, with medical grade signal quality on noise, electrode offset tolerance, common-mode rejection ratio, input impedance, and power dissipation, remains a challenging task. This paper reviews state-of-the-art bio-amplifier architectures and low-power analog circuits design techniques intended for wearable EEG acquisition, with a special focus on an AE system interfaced with dry electrodes.

Parallel processing via carbon field emission-based controlled-switching of regular bijective nano systolic networks, Part II

Purpose The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and their corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding many-valued (m-ary) extensions for the use in nano systolic networks are introduced. The second part of the paper introduces the implementation of systolic computing using two-to-one controlled switching via carbon-based field emission that were presented in the first part of the paper, and the computational extension to the general case of many-valued (m-ary) systolic networks utilizing many-to-one carbon-based field emission is also introduced. Design/methodology/approach The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field-emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented. Findings Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field-emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented. Practical implications The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power VLSI circuit design for signal processing applications. Originality/value The introduced bijective systolic implementations form new important directions in the systolic realizations utilizing the newly emerging nanotechnologies. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of high performance, minimum power and minimum size.

A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones

Conventional active noise cancelling (ANC) headphones often perform well in reducing the low-frequency noise and isolating the high-frequency noise by earmuffs passively. The existing ANC systems often use high-speed digital signal processors to cancel out disturbing noise, which results in high power consumption for a commercial ANC headphone. The contribution of this paper can be classified into: 1) proper filter length selection; 2) low-power storage mechanism for convolution operation; and 3) high-throughput pipelining architecture. With these novel techniques, we develop an area-/power-efficient ANC circuit by using the TSMC 90-nm CMOS technology for in-ear headphone applications. The proposed feedforward filtered-x least mean square ANC circuit design provides the features of using lower operating frequency and consuming much less power that facilitate better performance than the conventional ANC headphones. To verify the effectiveness of the proposed design, a series of physical measurements is executed in an anechoic chamber. Measurement results show that the proposed high-performance/low-power circuit design can reduce disturbing noise of various frequency bands very well, and outperforms the existing works. The proposed design can attenuate 15 dB for broadband pink noise between 50 and 1500 Hz when operated at 20-MHz clock frequency at the costs of 84.2 k gates and power consumption of 6.59 mW only. Compared with the existing designs, the proposed work achieves higher noise cancellation performance in terms of 3 dB further and saves 97% power consumption.

Comparative Analysis of Carbon Nanotube Field Effect Transistor and Nanowire Transistor for Low Power Circuit Design

Comparative Analysis of Carbon Nanotube Field Effect Transistor and Nanowire Transistor for Low Power Circuit Design

Delay Analysis of Half Subtractor using CMOS and Pass Transistor Logic

In present day skill, designing of low power systems has emerged as one of the vital theme of electronic industries due to the point that, power consumption is drawing much of the absorption in any very large scale integration (VLSI) chip design. Design of low power circuit for high performance is the necessary main concern of VLSI technique. This paper presents designing of Half Subtractor using basic gates which are drawn by conventional CMOS and Pass Transistor Logics based on 45nm technology . In comparison between the conventional CMOS half subtractor and using Pass Transistor Logic the delay is 10.5% less in PTLs half subtractor which is due to less number of transistors used in Pass Transistor Logic which in further has reduced the transistor count to 28.57%. Keywordssubtractor, pass transistor logic, digital circuits.

A Multi-Frequency Multi-Standard Wideband Fractional- PLL With Adaptive Phase-Noise Cancellation for Low-Power Short-Range Standards

This paper presents a wideband fractional- $ { N}$ frequency synthesizer design with a low-effort adaptive calibration technique for $\Sigma \Delta $ quantization noise cancellation. After adopting from the classical single-ended loop filter structure, this least mean square algorithm based calibration technique can precisely and efficiently adjust the noise cancellation digital–analog convertor current with high linearity and immunity. Besides, as long as the desired current is achieved, the calibration circuits are turned off and disconnected to save the power consumption and isolate from the signal paths. With the proposed phase-noise cancellation technique, small area and low power circuit design are achieved, meanwhile the fractional and reference spurs are highly attenuated, allowing the wideband direct frequency/phase modulation with high data rates. With low effort modification, it can be directly implemented as straightforward phase-noise enhancement for any wideband phase-locked loop applications.

Hierarchical Synthesis of Quantum and Reversible Architectures

Reversible hardware finds application in emerging areas such as low power circuit design, quantum computing, optical computing, and DNA computing. Intensive research has recently focused on the synthesis of quantum and reversible architectures. Quantum architectures often take advantage of reversible circuit synthesis methods but in general they require dedicated synthesis approaches because they represent a more general computing paradigm. Most of these quantum and reversible synthesis approaches derive efficient or even optimal circuits with scalability being their major drawback: they can only handle small circuits (up to a few hundred inputs for the most promising ones). In this paper, we propose a graph-based hierarchical synthesis method for large reversible and quantum architectures which can be combined with any of the existing synthesis methods to deliver unlimited scalability in synthesizing arbitrary large and irregular architectures. The specification of any complex function is provided in the form of a sequential algorithm consisting of primitive pre-synthesized operations available in a library. The components of the library may have been designed by ad-hoc methods or synthesized by the known methods in the literature or even by the proposed synthesis procedure. The synthesized architecture is represented as a dependence graph whose nodes correspond to the available components of the library and their respective inverses so as no garbage remains at the output. The method can be recursively applied at multiple levels to build any complex reversible or quantum architecture.