Low-power Circuit Design Research Articles

A hybrid magnetic/complementary metal oxide semiconductor process design kit for the design of low-power non-volatile logic circuits

Since the advent of the MOS transistor, the performance of microelectronic circuits has followed Moore’s law, stating that their speed and density would double every 18 months. Today, this trend tends to get out of breath: the continuously decreasing size of devices and increasing operation frequency result in power consumption and heating issues. Among the solutions investigated to circumvent these limitations, the use of non-volatile devices appears particularly promising. It allows easing, for example, the power gating technique, which consists in cutting-off the power supply of inactive blocks without losing information, drastically reducing the standby power consumption. In this approach, the advantages of magnetic tunnel junctions (MTJs) compared with other non-volatile devices allow one to design hybrid CMOS/magnetic circuits with high performance and new functionalities. Designing such circuits requires integrating MTJs in standard microelectronics design suites. This is performed by means of a process design kit (PDK) for the hybrid CMOS/magnetic technology. We present here a full magnetic PDK, which contains a compact model of the MTJ for electrical simulation, technology files for layout and physical verifications, and standard cells for the design of complex logic circuits and which is compatible with standard design suites. This PDK allows designers to accurately and comfortably design high-performance hybrid CMOS/magnetic logic circuits in the same way as standard CMOS circuits.

다치양자논리에 의한 다중제어 Toffoli 게이트의 실현

Multiple-control Toffoli(MCT) gates are macro-level multiple-valued gates needing quantum technology dependent primitive gates, and have been used in Galois Field sum-of-product (GFSOP) based synthesis of quantum logic circuit. Reversible logic is very important in quantum computing for low-power circuit design. This paper presents a reversible GF4 multiplier at first, and GF4 multiplier based quaternary MCT gate realization is also proposed. In the comparisons of MCT gate realization, we show the proposed MCT gate can reduce considerably primitive gates and delays in contrast to the composite one of the smaller MCT gates in proportion to the multiple-control input increase.

Design Low Voltage FGMOS Operational Amplifier for Power Applications

Due to the rise in demand for portable electronic device, low power and low voltage circuit design is extremely important for the appliances like computers, laptops, mobile phones and etc. Low power dissipation results in longer battery life and better integration density. This can be achieved by designing a modified low voltage op amp. The design of low voltage op amp in this paper is the combination of several low voltage analog cells. The modified low power op amp in this paper is built based on low voltage basic op amp. In this paper, the design objective is to achieve certain criteria such as supply voltage as low as 1 V, high gain more than 40 dB, low power consumption and high bandwidth. The use of FGMOS would increase the operating range of op amp through programming the threshold voltage of the FGMOS. This project is simulated using Silvaco Gateway and Expert.

Design of Low-power Wake-up Circuits in Underwater Acoustic Communication

Abstract In underwater acoustic communication, the power consumption of the underwater communication equipments at harsh conditions of marine environment is an important problem. Under that scenario, we propose a design of low-power wake-up circuits based on SCM C8051F020 system. Compare to traditional wake-up circuits which directly judge the energy of received signals, our approach can greatly reduce the misjudgment caused by the environmental disturbance, and the performance of energy conservation is effective. The low-power wake-up circuits possess a promising application prospect in the long-distance wireless underwater communication.

Security Frameworks for Wireless Sensor Networks-Review

Due to significant advances in miniaturization, low power circuit design but reasonably efficient to carry the sensitive information through wireless communication, wireless sensor network (WSN) have attracted attention a lot in recent years. WSN's are being used in many applications like health monitoring, military purposes, and home automation. Since WSN suffer from many constraints including lower processing power, low battery life, small memory and wireless communication channel, security becomes the main concern to deal with such kind of networks. Due to these well accepted limitations, WSN is not able to deal with traditional cryptographic algorithms. This paper gives an overview of cryptographic frameworks designed so far and also a comparison of existing schemes is tabled.

Content-Based LCD Backlight Power Reduction With Image Contrast Enhancement Using Histogram Analysis

In recent years, low-power technology has had a significant impact on portable electronic devices; with mobile devices, the low-power circuit design has become the primary issue. At present, thin-film transistor liquid crystal display (TFT LCD) is widely used in handheld mobile devices. In terms of the overall system power consumption, TFT LCD power consumes 20%-45% of total system power due to different applications. The backlight of an LCD display dominates the power consumption of the whole system; controlling the backlight current to reduce the brightness and the contrast of LCDs can reduce the overall power consumption. However, this may cause significant changes in visual perception. In order to reduce the power consumption and eliminate the visual changes, the issue becomes: how to reduce the current by adjusting brightness and contrast in accordance with the current image. Based on content analysis, this paper proposes two new algorithms: the new backlight-dimming algorithm (NBDA) and the new image enhancement algorithm (NIEA). The proposed methods can, on average, simultaneously reduce power consumption by 47% and improve the image enhancement ratio by 6.8%. Moreover, the structural-similarity index metric (SSIM) is used to evaluate image quality.

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

ASIC design of a high speed low power circuit for factorial calculation of a number is reported in this paper. The factorial of a number can be calculated using iterative multiplication by incrementing or decrementing process and iterative multiplication can be computed through parallel implementation methodology. Parallel implementation along with Vedic multiplication methodology for calculation of factorial of a number ensures significant reduction in propagation delay and switching power consumption due to reduction of stages in multiplication process, in comparison with the conventionally used Vedic multiplication methodologies like ‘Urdhva-tiryakbyham’ (UT) and ‘Nikhilam Navatascaramam Dasatah’ (NND) based implementation methodology. Transistor level implementation was carried out using spice specter with standard 90nm CMOS technology and the results were compared with the above mentioned conventional methodologies. The propagation delay for the calculation of 4-bit factorial of a number was only ∼42.13ns while the power consumption of the same was ∼58.82mW for a layout area of ∼6mm2. Improvement in speed was found to be ∼33% and ∼24% while corresponding reduction of power consumption in ∼34.48% and ∼24% for the factorial calculation circuitry in comparison with UT and NND based implementations, respectively.

Near-Threshold Computing of Clocked Adiabatic Logic with Complementary Pass-Transistor Logic Circuits

Low-power design already becomes the main challenge in the modern VLSI design community. The voltage scaling technique has proved to be one of the most effective methods for low-power circuit design. Although sub-threshold circuits can obtain extremely large energy savings, their performance penalty is huge. In this paper, we propose a new adiabatic logic named as CAL-CPL (Clocked Adiabatic Logic with Complementary Pass-transistor Logic) circuit. The CAL-CPL circuit is similar to CAL (Clocked Adiabatic Logic) expect for its logic evaluation tree that is constructed by using CPL module to replace the NMOS logic tree of CAL. The characteristic of the CAL-CPL circuits is analyzed in term of energy dissipations. Then the energy dissipation and performance of the CAL-CPL circuits are investigated by lowing supply voltage from nominal voltage to near-threshold voltage. In the near-threshold region, the CAL-CPL circuits obtain considerable energy savings with a little performance penalty. A 4-2 compressor and 8421 BCD up-counter based on CAL-CPL circuits are realized and simulated using HSPICE at a 45 nm CMOS process with the NCSU PTM model. Simulation results show that the average power consumption of the near-threshold 4-2 compressor and 8421 BCD up-counter are reduced about 24% and 32% compared with the super-threshold ones for clock rates ranging from 50 MHz to 400 MHz, respectively. Therefore, the near-threshold computing of CAL-CPL circuits is an attractive approach especially suiting for mid performance low-power applications.

Ultra Low-Power Algorithm Design for Implantable Devices: Application to Epilepsy Prostheses

Low-power circuit design techniques have enabled the possibility of integrating signal processing and feature extraction algorithms on-board implantable medical devices, eliminating the need for wireless transfer of data outside the patient. Feature extraction algorithms also serve as valuable tools for modern-day artificial prostheses, made possible by implantable brain-computer-interface systems. This paper intends to review the challenges in designing feature extraction blocks for implantable devices, with specific focus on developing efficacious but computationally efficient algorithms to detect seizures. Common seizure detection features used to construct algorithms are evaluated and algorithmic, mathematical as well as circuit-level design techniques are suggested to effectively translate the algorithms into hardware implementations on low-power platforms.

Ultralow-Power Operation in Subthreshold Regimes Applying Clockless Logic

Energy performance requirements are causing designers of next-generation systems to explore approaches to lowest possible power consumption. Subthreshold operation is being examined to stretch low-power circuit designs beyond the normal modes of operation, with the potential for large energy savings. Some of the challenges to be overcome, like 10-100× performance penalties, are being addressed by research into parallelism. However, the uncertainty in timing generated by operating in subthreshold represents a major challenge to overcome. In this paper, first, we will introduce some background information on digital logic subthreshold operation, then provide some background on clockless logic design approaches giving a brief overview of some of the characteristics of the different design styles and focusing on NULL convention logic. Next, we will examine the application of that clockless logic approach to a military system, reviewing the background of the experiment, factors considered in the comparison, and then summarizing the results of the comparisons. Finally, an overview of additional research and development that will be needed to make the technique available to subthreshold designers is presented.

Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link

A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the high-frequency performance of the rectifier block. Test chips are fabricated in a 0.18µm CMOS process. With a pair of 700 × 700µm2 on-chip inductors, the test chips achieve 10% peak efficiency and 36mW power transmission. Compared with the previous work the received power is 13 times larger for the same inductor size [7].

REVERSIBLE VITERBI ALGORITHM AND ITS CLOSED-SYSTEM Q-DOMAIN CIRCUIT DESIGN AND COMPUTATION

Novel convolution-based multiple-stream error-control coding and decoding methods and their corresponding circuits are introduced. The new coding method applies the reversibility property in (1) the convolution-based encoder for multiple-stream error-control encoding and (2) in the new reversible Viterbi decoding algorithm for multiple-stream error-correction decoding. The complete synthesis of quantum circuits for the quantum realization of the new quantum Viterbi cell in the quantum domain (Q-domain) is also introduced, and the associated quantum computing representations and operations are presented. In quantum mechanics, a closed system is an isolated system that cannot exchange energy or matter with its surroundings and does not interact with other quantum systems. Closed quantum systems obey the unitary evolution and thus they are reversible. Reversibility property in error-control coding can be important for the following main reasons: (1) reversibility is a basic requirement for low-power circuit design in future technologies such as in closed-system quantum computing (QC), (2) reversibility leads to super-speedy encoding/decoding operations because of the superposition and entanglement properties that exist in the reversible closed-system quantum computing circuits and systems, and (3) the reversibility relationship between multiple-streams of data can be used for the correction of errors that are usually uncorrectable using the implemented decoding algorithm such as in the case of triple-errors that are uncorrectable using the irreversible Viterbi algorithm.

Automatic Design of Low-Power Low-Voltage Analog Circuits Using Particle Swarm Optimization with Re-Initialization

In this paper, we present application and effectiveness of Particle Swarm Optimization (PSO) for automatic sizing of analog circuits. An efficient re-initialization strategy is introduced to improve the performance of PSO Algorithm (referred as PSO-R). Four benchmark circuits, namely, (i) CMOS buffer chain, (ii) two-stage CMOS operational amplifier (op-amp), (iii) high-gain low-power low-voltage three-stage CMOS op-amp, and (iv) a recently reported ultra-low-power ultra-low-voltage CMOS Miller operational transconductance amplifier (OTA), are automatically designed using the PSO-R algorithm. For the purpose of comparison, these circuits are also designed using PSO, Hierarchical PSO (HPSO), and Genetic Algorithm (GA). Various CMOS technologies ranging from 0.35 μm down to 0.13 μm are used. PVT (process, voltage, and temperature) variations are taken into account and Spectre tool is used for circuit simulations. The PSO-R algorithm converges to a better solution compared to other algorithms for multiple design trials of various low-power low-voltage op-amp designs. For CMOS ultra-low-power ultra-low-voltage Miller OTA, even performance of the circuit designed by the PSO-R algorithm is better than that of recently reported manual design of the same circuit. For future ultra-low-voltage applications, this OTA is also designed in 0.4 V supply voltage. This 0.4 V OTA gives a DC gain of 75 dB, unity gain frequency of 50 MHZ, and dissipates a power of 550 nW. For this design, PSO-R algorithm has taken 19 minutes of CPU time on average on a Sun system with 1.2 GHz dual core processor and 8 GB RAM.

The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control

An inductor-less on-chip micro power management system for light energy harvesting applications is presented. We target at wide variety of applications that operate at different lighting environments ranging from strong sunlight to dim indoor lighting where the output voltage from the photovoltaic cells is low. A step-up charge pump is used to directly operate the circuit or to charge a rechargeable battery. The power management system operation is discussed and the control strategy for transferring the maximum output power from the power system is presented. Low power circuit design is proposed for the implementation of the system maximum output power control. The system was implemented using a 0.35-mum CMOS process. The chip was fabricated and measurements were conducted for different lighting conditions to demonstrate the system operation and verify the control strategy.

A Biomimetic, 4.5 $\mu$W, 120+ dB, Log-Domain Cochlea Channel With AGC

This paper deals with the design and performance evaluation of a new analog CMOS cochlea channel of increased biorealism. The design implements a recently proposed transfer function, namely the One-Zero Gammatone filter (or OZGF), which provides a robust foundation for modeling a variety of auditory data such as realistic passband asymmetry, linear low-frequency tail and level-dependent gain. Moreover, the OZGF is attractive because it can be implemented efficiently in any technological medium-analog or digital-using standard building blocks. The channel was synthesized using novel, low-power, class-AB, log-domain, biquadratic filters employing MOS transistors operating in their weak inversion regime. Furthermore, the paper details the design of a new low-power automatic gain control circuit that adapts the gain of the channel according to the input signal strength, thereby extending significantly its input dynamic range. We evaluate the performance of a fourth-order OZGF channel (equivalent to an 8th-order cascaded filter structure) through both detailed simulations and measurements from a fabricated chip using the commercially available 0.35 mum AMS CMOS process. The whole system is tuned at 3 kHz, dissipates a mere 4.46 muW of static power, accommodates 124 dB (at < 5% THD) of input dynamic range at the center frequency and is set to provide up to 70 dB of amplification for small signals.

Closed-system quantum logic network implementation of the Viterbi algorithm

New convolution-based multiple-stream error-control coding and decoding schemes are introduced. The new coding method applies the reversibility property in the convolution-based encoder for multiple-stream error-control encoding and implements the reversibility property in the new reversible Viterbi decoding algorithm for multiple-stream error-correction decoding. The complete design of quantum circuits for the quantum realization of the new quantum Viterbi cell in the quantum domain is also introduced. In quantum mechanics, a closed system is an isolated system that can't exchange energy or matter with its surroundings and doesn't interact with other quantum systems. In contrast to open quantum systems, closed quantum systems obey the unitary evolution and thus they are reversible. Reversibility property in error-control coding can be important for the following main reasons: (1) reversibility is a basic requirement for low-power circuit design in future technologies such as in quantum computing (QC), (2) reversibility leads to super-speedy encoding/decoding operations because of the superposition and entanglement properties that emerge in the quantum computing systems that are naturally reversible and therefore very high performance is obtained, and (3) it is shown in this paper that the reversibility relationship between multiple-streams of data can be used for further correction of errors that are uncorrectable using the implemented decoding algorithm such as in the case of triple-errors that are uncorrectable using the classical irreversible Viterbi algorithm. .

Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems

The implementation of complex, high-performance functionalities in low-power nano-CMOS technologies faces significant design and test challenges related to the increased susceptibility to environmental or operation-dependent disturbances, process variations or emerging defect types. This paper describes the application of semi-empirical propagation delay variation models to support the design and test of low-power nanometer digital circuits, taking into account these challenging issues. Results are presented demonstrating that the models provide designers and test engineers with a powerful tool to analytically account for all effects leading to delay faults. They can be used to define parametric delay tests, as well as to design circuits with increased robustness to delay faults under low-power operation. Its derivation and application can be easily automated, allowing them to be integrated in standard flows.

Photovoltaic scavenging systems: Modeling and optimization

The interest in embedded portable systems and wireless sensor networks (WSNs) that scavenge energy from the environment has been increasing over the last years. Thanks to the progress in the design of low-power circuits, such devices consume less and less power and are promising candidates to perform continued operation by the use of renewable energy sources. The adoption of maximum power point tracking (MPPT) techniques in photovoltaic scavengers increases the energy harvesting efficiency and leads to several benefits such as the possibility to shrink the size of photovoltaic modules and energy reservoirs. Unfortunately, the optimization of this process under non-stationary light conditions is still a key design challenge and the development of a photovoltaic harvester has to be preceded by extensive simulations. We propose a detailed model of the solar cell that predicts the instantaneous power collected by the panel and improves the simulation of harvester systems. Furthermore, the paper focuses on a methodology for optimizing the design of MPPT solar harvesters for self-powered embedded systems and presents improvements in the circuit architecture with respect to our previous implementation. Experimental results show that the proposed design guidelines allow to increment global efficiency and to reduce the power consumption of the scavenger.

Ultra-low-power biopotential interfaces and their applications in wearable and implantable systems

Traditionally the monitoring of the biopotential signals are only limited to clinical applications. On the other hand, there is a growing demand for these biopotential signals to be used in non-clinical applications in order to improve the quality of life and enable the interaction between humans and machines. However, such non-clinical applications of biopotential signal monitoring requires various improvements not only in terms of size and comfort of the biopotential acquisition systems, but also in terms of their power dissipation. An important building block of the biopotential acquisition systems is the front-end circuitry that defines the quality of the extracted signals and unfortunately consumes unacceptable power, when the currently available circuitry is considered. Therefore, this paper focuses on the advances in low-power and high-performance readout circuit design for the acquisition of biopotential signals. In addition, several application examples will be demonstrated, which proves that the realization of high-performance and low-power readout circuits can actually enable the implementation of miniaturized and comfortable biopotential acquisition systems extending the usage of such systems towards non-clinical applications.

Tunable Highly Linear Floating-Gate CMOS Resistor Using Common-Mode Linearization Technique

In this paper, an implementation of a tunable highly linear floating resistor that can be fully integrated in CMOS technology is presented. The second-order effects of a single MOS transistor operating in the triode operation regime are described, and a common-mode linearization technique is applied to suppress these nonlinearities. This technique is implemented by utilizing a low-power circuit design strategy that exploits the capacitive coupling and the charge storage properties of floating-gate transistors. The resistance of the proposed circuit is tuned by utilizing the Fowler-Nordheim tunneling and hot-electron injection quantum-mechanical phenomena. We demonstrate the use of this resistor in highly linear amplifier. We present experimental data from the chips that were fabricated in a 0.5- CMOS process. We show that this resistor exhibits 0.024% total harmonic distortion (THD) for a sine wave with amplitude. Also, we show the programmability of the amplifier gain using the proposed tunable resistor.