Low Off-currents Research Articles

Modeling tunnel currents in organic permeable-base transistors

Research in organic permeable base transistors (OPBTs) has led to a significant increase in their performance. However, despite this progress, understanding of the working mechanism of OPBTs is still limited. Although first numerical models of OPBTs are able to describe the switching mechanism of OPBTs correctly, they neglect currents injected at the base electrode, which leads to unrealistically low off-currents and high ON/OFF ratios.Here, a tunneling model is developed that is capable of describing injection of charges through a thin oxide layer formed around the base electrode of OPBTs. With the help of this injection model, the performance of the base–collector diode of OPBTs is discussed. In particular, the model is used to explain the reduction in backward currents due to an exposure to ambient air by an increase in the thickness of the oxide layer. Furthermore, the tunnel model is used to show that the reduction in backward currents of the base–collector diode leads to a decrease in off-currents of complete OPBTs, which in turn leads to an increase in their ON/OFF ratio.

Cyano-Substituted Head-to-Head Polythiophenes: Enabling High-Performance n-Type Organic Thin-Film Transistors.

Polythiophenes, built on the electron-rich thiophene unit, typically possess high-lying energy levels of the lowest unoccupied molecular orbitals (LUMOs) and show hole-transporting properties. In this study, we develop a series of n-type polythiophenes, P1-P3, based on head-to-head-linked 3,3'-dialkoxy-4,4'-dicyano-2,2'-bithiophene (BTCNOR) with distinct side chains. The BTCNOR unit shows not only highly planar backbone conformation enabled by the intramolecular noncovalent sulfur-oxygen interaction but also significantly suppressed LUMO level attributed to the cyano-substitution. Hence, all BTCNOR-based polymer semiconductors exhibit low-lying LUMO levels, which are ∼1.0 eV lower than that of regioregular poly(3-hexylthiophene) (rr-P3HT), a benchmark p-type polymer semiconductor. Consequently, all of the three polymers can enable unipolar n-type transport characteristics in organic thin-film transistors (OTFTs) with low off-currents ( Ioffs) of 10-10-10-11 A and large current on/off ratios ( Ion/ Ioffs) at the level of 106. Among them, polymer P2 with a 2-ethylhexyl side chain offers the highest film ordering, leading to the best device performance with an excellent electron mobility (μe) of 0.31 cm2 V-1 s-1 in off-center spin-cast OTFTs. To the best of our knowledge, this is the first report of n-type polythiophenes with electron mobility comparable to the hole mobility of the benchmark p-type rr-P3HT and approaching the electron mobility of the most-studied n-type polymer, poly(naphthalene diimide- alt-bithiophene) (i.e., N2200). The change of charge carrier polarity from p-type (rr-P3HT) to n-type (P2) with comparable mobility demonstrates the obvious effectiveness of our structural modification. Adoption of n-hexadecyl (P1) and 2-butyloctyl (P3) side chains leads to reduced film ordering and results in 1-2 orders of magnitude lower μes, showing the critical role of side chains in optimizing device performance. This study demonstrates the unique structural features of head-to-head linkage containing BTCNOR for constructing high-performance n-type polymers, i.e., the alkoxy chain for backbone conformation locking and providing polymer solubility as well as the strong electron-withdrawing cyano group for lowering LUMO levels and enabling n-type performance. The design strategy of BTCNOR-based polymers provides useful guidelines for developing n-type polythiophenes.

Two-Terminal Multibit Optical Memory via van der Waals Heterostructure.

2D van der Waals (vdWs) heterostructures exhibit intriguing optoelectronic properties in photodetectors, solar cells, and light-emitting diodes. In addition, these materials have the potential to be further extended to optical memories with promising broadband applications for image sensing, logic gates, and synaptic devices for neuromorphic computing. In particular, high programming voltage, high off-power consumption, and circuital complexity in integration are primary concerns in the development of three-terminal optical memory devices. This study describes a multilevel nonvolatile optical memory device with a two-terminal floating-gate field-effect transistor with a MoS2 /hexagonal boron nitride/graphene heterostructure. The device exhibits an extremely low off-current of ≈10-14 A and high optical switching on/off current ratio of over ≈106 , allowing 18 distinct current levels corresponding to more than four-bit information storage. Furthermore, it demonstrates an extended endurance of over ≈104 program-erase cycles and a long retention time exceeding 3.6 × 104 s with a low programming voltage of -10 V. This device paves the way for miniaturization and high-density integration of future optical memories with vdWs heterostructures.

Low-frequency noise analysis of heterojunction SELBOX TFET

This paper explores low-frequency noise analysis of TFET on selective buried oxide (SELBOX) with a δp + silicon germanium layer at the source channel junction in the presence of uniform and gaussian trap concentrations. Different electrical parameters of the proposed structure for the optimized position of gap are investigated. Lowest OFF current is obtained for the position of gap near the source region. Considering the current noise spectral density (SID) and voltage noise spectral density (SVG), the impact of noise on the device performance is analyzed. Noise spectral densities are compared in the presence of interface trap concentrations and δp+ Si1−xGex layer Ge-mole fractions. Variation of noise densities with frequency is explored. Improved ION/IOFF ratio and subthreshold swing are obtained in the presence of uniform trap as compared to gaussian trap.

Realizing Bidirectional Threshold Switching in Ag/Ta2O5/Pt Diffusive Devices for Selector Applications

Memristor crossbar arrays have great potential in brain inspired computing and the next generation high-density memories. The sneak current issue, however, seriously degrades their performance with increasing array size. Selectors with volatile threshold switching (TS) behavior have become important components of the arrays to suppress this issue. Ag/Ta2O5/Pt diffusive devices have promising TS characteristics as selectors, including high ON/OFF ratio and low OFF current. However, their unidirectional TS excludes their application in arrays consisting of bipolar memristors. Bipolar memristors require voltage biases of different polarities to enable the device programming, thus selectors with bidirectional TS are essential for them. In this study, we realize reproducible bidirectional TS behavior on Ag/Ta2O5/Pt diffusive devices. The ON/OFF ratio and the OFF current of the device are ∼107 A and ∼ 10−12 A, respectively. The switching voltage is ∼ 0.35 V and the hold voltage is ∼ 0.125 V. The TS behavior can be also optimized by choosing suitable compliance current during a voltage sweep. Simulations of nanoparticles diffusion are also carried out to study the mechanism of this bidirectional TS process. The simulations show that this behavior can be attributed to the outer diffusion of Ag nanoparticles from an Ag electrode and their accumulation near the Pt electrode under the voltage sweep, which can serve as an additional counter active electrode. This work illustrates that Ag/Ta2O5/Pt diffusive devices are promising candidates for selector applications in bipolar memristor crossbar arrays.

Ag:SiO xN y-Based Bilayer ReRAM Structure with Self-Limiting Bidirectional Threshold Switching Characteristics for Cross-Point Array Application.

We fabricate a Pt/Ag:SiO xN y/Ti programmable metallization cell exhibiting bidirectional threshold switching (TS) or nonvolatile resistive switching (RS) characteristics through a simple thermal annealing process. The cell composed of pristine Ag:SiO xN y layers showed self-limiting TS characteristics with high selectivity and extremely low OFF currents, whereas the same cell showed typical RS characteristics after thermal annealing at 250 °C. The operating mechanism was investigated using scanning transmission electron microscopy and X-ray photoelectron spectroscopy. Next, a Ag:SiO xN y-based one selector-one resistor device was fabricated by employing both TS and RS characteristics in a single cell, which exhibited excellent self-rectifying memory performance.

Corrugated Heterojunction Metal-Oxide Thin-Film Transistors with High Electron Mobility via Vertical Interface Manipulation.

A new strategy is reported to achieve high-mobility, low-off-current, and operationally stable solution-processable metal-oxide thin-film transistors (TFTs) using a corrugated heterojunction channel structure. The corrugated heterojunction channel, having alternating thin-indium-tin-zinc-oxide (ITZO)/indium-gallium-zinc-oxide (IGZO) and thick-ITZO/IGZO film regions, enables the accumulated electron concentration to be tuned in the TFT off- and on-states via charge modulation at the vertical regions of the heterojunction. The ITZO/IGZO TFTs with optimized corrugated structure exhibit a maximum field-effect mobility >50 cm2 V-1 s-1 with an on/off current ratio of >108 and good operational stability (threshold voltage shift <1 V for a positive-gate-bias stress of 10 ks, without passivation). To exploit the underlying conduction mechanism of the corrugated heterojunction TFTs, a physical model is implemented by using a variety of chemical, structural, and electrical characterization tools and Technology Computer-Aided Design simulations. The physical model reveals that efficient charge manipulation is possible via the corrugated structure, by inducing an extremely high carrier concentration at the nanoscale vertical channel regions, enabling low off-currents and high on-currents depending on the applied gate bias.

Enhancement-Mode AlN/GaN HEMTs With High Ion/Ioff and Low-Leakage-Current Fabricated With Low-Power Surface Oxidation Treatment

Low leakage current enhancement-mode (E-mode) AlN/GaN high-electron mobility transistors (HEMTs) have been successfully fabricated using low-power surface oxidation treatment (LP-SOT). The oxidation treatment resulted in a reduction of channel electron gas and gate leakage current. The AlN/GaN HEMTs and MOSHEMTs all exhibit a low leakage current, large Ion/Ioff, low subthreshold swing (SS), and low interface states. The record positive threshold voltage ( ${V}_{\textsf {th}}$ ) of 0.2 V, considerably large maximum drain current of 1.36 A/mm, low off-current of $\textsf {2.6} \times \textsf {10}^{-\textsf {7}}$ A/mm, large Ion/Ioff of $\textsf {4}\times \textsf {10}^{\textsf {6}}$ , and low SS of 70 mV/dec were achieved for E-mode AlN/GaN HEMTs. The high maximum drain current and positive $\textsf {V}_{\textsf {th}}$ were attributed to large sheet electron density difference of samples with LP-SOT before and after deposition of an Al2O3 dielectric layer.

(Semi)ladder-Type Bithiophene Imide-Based All-Acceptor Semiconductors: Synthesis, Structure-Property Correlations, and Unipolar n-Type Transistor Performance.

Development of high-performance unipolar n-type organic semiconductors still remains as a great challenge. In this work, all-acceptor bithiophene imide-based ladder-type small molecules BTI n and semiladder-type homopolymers PBTI n ( n = 1-5) were synthesized, and their structure-property correlations were studied in depth. It was found that Pd-catalyzed Stille coupling is superior to Ni-mediated Yamamoto coupling to produce polymers with higher molecular weight and improved polymer quality, thus leading to greatly increased electron mobility (μe). Due to their all-acceptor backbone, these polymers all exhibit unipolar n-type transport in organic thin-film transistors, accompanied by low off-currents (10-10-10-9 A), large on/off current ratios (106), and small threshold voltages (∼15-25 V). The highest μe, up to 3.71 cm2 V-1 s-1, is attained from PBTI1 with the shortest monomer unit. As the monomer size is extended, the μe drops by 2 orders to 0.014 cm2 V-1 s-1 for PBTI5. This monotonic decrease of μe was also observed in their homologous BTI n small molecules. This trend of mobility decrease is in good agreement with the evolvement of disordered phases within the film, as revealed by Raman spectroscopy and X-ray diffraction measurements. The extension of the ladder-type building blocks appears to have a large impact on the motion freedom of the building blocks and the polymer chains during film formation, thus negatively affecting film morphology and charge carrier mobility. The result indicates that synthesizing building blocks with more extended ladder-type backbone does not necessarily lead to improved mobilities. This study marks a significant advance in the performance of all-acceptor-type polymers as unipolar electron transporting materials and provides useful guidelines for further development of (semi)ladder-type molecular and polymeric semiconductors for applications in organic electronics.

DESIGN OPTIMIZATION OF EXTREMELY SHORT-CHANNEL GRADED SI/SIGE HETEROJUNCTION TUNNEL FIELD-EFFECT TRANSISTORS FOR LOW POWER APPLICATIONS

This study investigates, by a two-dimensional simulation, the design optimization of a proposed 8 nm tunnel field-effect transistor (TFET) for low standby power (LSTP) applications utilizing graded Si/SiGe heterojunction with device parameters based on the ITRS specifications. The source Ge mole fraction should be designed approximately 0.8 because using lower Ge fractions causes severe short-channel effects while with higher values does not significantly improve the device performance but may create big difficulties in fabrication. Based on simultaneously optimizing the subthreshold swing, on- and off-currents, optimum values of source doping, drain doping and length of the proposed device are approximately 1020 cm-3, 1018 cm-3, and 10 nm, respectively. The 8 nm graded Si/SiGe TFET with optimized device parameters demonstrates high on-current of 360 μA/μm, low off-current of 0.5 pA/μm, low threshold voltage of 85 mV and very steep subthreshold swing of sub-10 mV/decade. The designed TFET with graded Si/SiGe heterojunction exhibits an excellent performance and makes it an attractive candidate for future LSTP technologies because of its reality to be fabricated with existing FET and SiGe growth techniques.

Thiazole Imide-Based All-Acceptor Homopolymer: Achieving High-Performance Unipolar Electron Transport in Organic Thin-Film Transistors.

High-performance unipolar n-type polymer semiconductors are critical for advancing the field of organic electronics, which relies on the design and synthesis of new electron-deficient building blocks with good solubilizing capability, favorable geometry, and optimized electrical properties. Herein, two novel imide-functionalized thiazoles, 5,5'-bithiazole-4,4'-dicarboxyimide (BTzI) and 2,2'-bithiazolothienyl-4,4',10,10'-tetracarboxydiimide (DTzTI), are successfully synthesized. Single crystal analysis and physicochemical study reveal that DTzTI is an excellent building block for constructing all-acceptor homopolymers, and the resulting polymer poly(2,2'-bithiazolothienyl-4,4',10,10'-tetracarboxydiimide) (PDTzTI) exhibits unipolar n-type transport with a remarkable electron mobility (μe ) of 1.61 cm2 V-1 s-1 , low off-currents (Ioff ) of 10-10 -10-11 A, and substantial current on/off ratios (Ion /Ioff ) of 107 -108 in organic thin-film transistors. The all-acceptor homopolymer shows distinctive advantages over prevailing n-type donor-acceptor copolymers, which suffer from ambipolar transport with high Ioff s > 10-8 A and small Ion /Ioff s < 105 . The results demonstrate that the all-acceptor approach is superior to the donor-acceptor one, which results in unipolar electron transport with more ideal transistor performance characteristics.

A Hybrid Gate Dielectrics of Ion Gel with Ultra-Thin Passivation Layer for High-Performance Transistors Based on Two-Dimensional Semiconductor Channels

We propose a hybrid gate structure for ion gel dielectrics using an ultra-thin Al2O3 passivation layer for realizing high-performance devices based on electric-double-layer capacitors. Electric-double-layer transistors can be applied to practical devices with flexibility and transparency as well as research on the fundamental physical properties of channel materials; however, they suffer from inherent unwanted leakage currents between electrodes, especially for channel materials with low off-currents. Therefore, the Al2O3 passivation layer was introduced between the metal electrodes and ion gel film as a leakage current barrier; this simple approach effectively reduced the leakage current without capacitance degradation. In addition, we confirmed that a monolayer MoS2 transistor fabricated with the proposed hybrid gate dielectric exhibited remarkably enhanced device properties compared to a transistor using a normal ion gel gate dielectric. Our findings on a simple method to improve the leakage current properties of ion gels could be applied extensively to realize high-performance electric-double-layer transistors utilizing various channel materials.

A sub-thermionic MoS2 FET with tunable transport

The inability to scale supply voltage and hence reduce power consumption remains a serious challenge in modern nanotransistors. This arises primarily because the Sub-threshold Swing (SS) of the thermionic MOSFET, a measure of its switching efficiency, is restricted by the Boltzmann limit (kBT/q = 60 mV/dec at 300 K). Tunneling FETs, the most promising candidates to circumvent this limit, employ band-to-band tunneling, yielding very low OFF currents and steep SS but at the expense of severely degraded ON currents. In a completely different approach, by introducing concurrent tuning of thermionic and tunneling components through metal/semiconductor Schottky junctions, we achieve an amalgamation of steep SS and high ON currents in the same device. We demonstrate sub-thermionic transport sustained up to 4 decades with SSmin ∼ 8.3 mV/dec and SSavg ∼ 37.5(25) mV/dec for 4(3) dec in few layer MoS2 dual gated FETs (planar and CMOS compatible) using tunnel injected Schottky contacts for a highly scaled drain voltage of 10 mV, the lowest for any sub-thermionic devices. Furthermore, the same devices can be tuned to operate in the thermionic regime with a field effect mobility of ∼84.3 cm2 V−1 s−1. A detailed mechanism involving the independent control of the Schottky barrier height and width through efficient device architecture and material processing elucidates the functioning of these devices. The Gate Tunable Thermionic Tunnel FET can function at a supply voltage of as low as 0.5 V, reducing power consumption dramatically.

Vertical InAs/InGaAs Heterostructure Metal-Oxide-Semiconductor Field-Effect Transistors on Si.

III-V compound semiconductors offer a path to continue Moore's law due to their excellent electron transport properties. One major challenge, integrating III-V's on Si, can be addressed by using vapor-liquid-solid grown vertical nanowires. InAs is an attractive material due to its superior mobility, although InAs metal-oxide-semiconductor field-effect transistors (MOSFETs) typically suffer from band-to-band tunneling caused by its narrow band gap, which increases the off-current and therefore the power consumption. In this work, we present vertical heterostructure InAs/InGaAs nanowire MOSFETs with low off-currents provided by the wider band gap material on the drain side suppressing band-to-band tunneling. We demonstrate vertical III-V MOSFETs achieving off-current below 1 nA/μm while still maintaining on-performance comparable to InAs MOSFETs; therefore, this approach opens a path to address not only high-performance applications but also Internet-of-Things applications that require low off-state current levels.

Impact ionization and tunneling operations in charge-plasma dopingless device

In this paper, we present the impact ionization and tunneling operations in a newly designed dopingless device. Our proposed device functions selectively—as either a p-channel impact-ionization MOSFET (p-IMOS) or an n-channel tunneling field-effect transistor (n-TFET)—according to the bias conditions. To realize the dopingless device, the charge-plasma effect is employed to induce n- or p-type regions without any doping process, by choosing an electrode metal with an appropriate work function. The band diagrams, I–V characteristics, subthreshold swings (SS), and carrier-concentration profiles of the device under the p-IMOS and n-TFET operation modes are analyzed in our study, using a commercial device simulator. The device yields an extremely low SS of 0.53 mV/dec under the p-IMOS operation mode. It also exhibits a low off-current of approximately 10−14 A/μm and a high ION/IOFF of approximately 108, under the n-TFET operation mode.

Comparative study on growth characteristics and electrical properties of ZrO2 films grown using pulsed plasma-enhanced chemical vapor deposition and plasma-enhanced atomic layer deposition for oxide thin film transistors

The deposition of high-quality ZrO2 films has been achieved using both pulsed plasma-enhanced chemical vapor deposition (P-PE-CVD) and plasma-enhanced atomic layer deposition (PE-ALD) with (C5H5)Zr[N(CH3)2]3 as a Zr precursor. The authors compared the growth characteristics, chemical compositions, and electrical properties of P-PE-CVD and PE-ALD ZrO2 prepared under various deposition conditions. The ZrO2 films prepared using both methods showed high purity and good stoichiometry. Electrical characterization of a metal-oxide-semiconductor capacitor utilizing the ZrO2 films showed that PE-ALD films have a relatively lower leakage current than P-PE-CVD films, whereas the dielectric constant, interface trap density, and hysteresis of both films are similar. Applying both methods, the electrical properties of ZrO2 films were also evaluated using In–Ga–Zn–O thin-film transistors (TFTs), which showed a good device performance in terms of high Ion-Ioff ratios (&amp;gt;108) and low off-currents (&amp;lt;10−11 A). In addition, ZrO2-based TFT showed high reliability against a negative Vth shift. Based on the self-limiting growth characteristics and electrical properties of P-PE-CVD, the authors found that the P-PE-CVD process results in electrical properties comparable to those of PE-ALD ZrO2 films. Thus, the authors believe that P-PE-CVD can be an alternative process to PE-ALD for future electronic device applications, especially for display applications due to its good electrical properties with high throughput.

Steep subthreshold slope characteristics of body tied to gate NMOSFET in partially depleted SOI

A new body tied to gate (BTG) n-channel metal-oxide-semiconductor field-effect-transistor (NMOSFET) with a diode in partially depleted SOI (PD SOI) is proposed and investigated. We first compare the transfer and output characteristics between the regular and BTG NMOSFETs with grounded body and floating body. The steep subthreshold slope (<6mV/dec) and low OFF current (∼0.01pA/μm) of the BTG NMOSFET with floating body are observed at VD=3.3V. Mechanisms of the floating body effect (FBE) and the diode are analyzed to explain the outstanding performance. The hysteresis characteristics of BTG NMOSFETs are also presented in comparison to regular ones. Finally, the steep subthreshold characteristics of the BTG NMOSFET with floating body at low drain voltage are studied for ultralow power application.

Gate All Around Nanowire TFET with High ON/OFF Current Ratio

The serious thermal management crises in the next generation digital systems due to power dissipation boom are limited by the reduction in supply voltage. Transistors with lower Subthreshold Slopes (SS) are needed for low power systems. Recent years Tunnel Field Effect Transistors (TFETs) are good alternatives for the existing MOSFETs to cope up with the continuous scaling down of device dimensions. TFETs have reduced Short Channel Effects (SCE), low OFF currents (IOFF) and small SS. But, the major drawback of TFETs is their considerably low ON current (ION). The simplest solution to this problem is a Double Gate (DG) structure, instead of a Single Gate (SG), which will provide ION improvement. A Gate All Around (GAA) structure is the ultimate solution for the improvement of IOFF and ION/IOFF current ratio due to its excellent gate coupling. In this paper a GAA nanowire TFET with a channel length of 32 nm having high ION/IOFF ratio is modelled.

MoS2 Field-Effect Transistor with Sub-10 nm Channel Length.

Atomically thin molybdenum disulfide (MoS2) is an ideal semiconductor material for field-effect transistors (FETs) with sub-10 nm channel lengths. The high effective mass and large bandgap of MoS2 minimize direct source-drain tunneling, while its atomically thin body maximizes the gate modulation efficiency in ultrashort-channel transistors. However, no experimental study to date has approached the sub-10 nm scale due to the multiple challenges related to nanofabrication at this length scale and the high contact resistance traditionally observed in MoS2 transistors. Here, using the semiconducting-to-metallic phase transition of MoS2, we demonstrate sub-10 nm channel-length transistor fabrication by directed self-assembly patterning of mono- and trilayer MoS2. This is done in a 7.5 nm half-pitch periodic chain of transistors where semiconducting (2H) MoS2 channel regions are seamlessly connected to metallic-phase (1T') MoS2 access and contact regions. The resulting 7.5 nm channel-length MoS2 FET has a low off-current of 10 pA/μm, an on/off current ratio of >107, and a subthreshold swing of 120 mV/dec. The experimental results presented in this work, combined with device transport modeling, reveal the remarkable potential of 2D MoS2 for future sub-10 nm technology nodes.

An Ultra-Short Channel Monolayer MoS2 FET Defined By the Curvature of a Thin Nanowire

In this letter, we demonstrate the first top-gated 10-nm scale field-effect transistor with chemical-vapor-deposition synthesized monolayer MoS2 as the channel material. Ultra-thin metallic Co2Si nanowires are employed to gate the MoS2 channel and thereby define the device feature size—gate/channel length, as well as to serve as a self-aligned mask for source/drain metallization. This process not only avoids using the high-cost and low-yield electron beam lithography to define the gate/channel length, but also enables a top-gate structure with ultrathin gate dielectric. The latter is required to suppress short channel effects, but difficult to achieve with conventional deposition techniques on 2D layered semiconductors. Moreover, low OFF-current of 10 pA/ $\mu \text{m}$ and high ON/OFF current ratio over six orders are achieved, which makes this device quite promising for next-generation CMOS technology.