Recent progress on negative capacitance tunnel FET for low-power applications: Device perspective

Abstract

In the present-day scenario of low-power electronics, there is a steady and increasing need for an adequate device that can counteract the power dissipation issue due to the consistent scaling of device dimensions. For this purpose, the evolution of low subthreshold swing (SS) based devices, especially with the negative capacitance (NC) techniques, has presented a well-favored solution. The NC of ferroelectrics (FE) materials could be widely utilized to provide the gate voltage (VG) amplification under specific conditions to boost the performance of the MOS device, by addressing the ultimate fundamental limitation of Boltzmann Tyranny and offering the SS much lower than 60mV/dec. Along with the advent of this state-of-art NC technology, tunnel field-effect transistor (TFET) also emerges for accomplishing low SS and becomes one of the promising techniques for low-power applications. Incorporating these two principles (NC and tunneling) into a single device architecture enables the super-steep SS and remarkably low OFF current (IOFF). This cutting-edge combination, negative capacitance tunnel FET (NC-TFET) device has opened up the possibility of an ultra-low-power and high-performance device. This review paper mainly focuses on the theoretical background and recent progress in the field of NC-TFET with abundant quantum-mechanical models and various perspectives such as transistor perspective, analog circuit perspective, and future road map perspective.