Low-k Dielectric Materials Research Articles

Row hammer-induced D0 failure improvement in sub-20 nm DRAM using air gap

Abstract As the density of bit cells increases, reliability issue in state-of-the-art Dynamic Random Access Memory (DRAM) becomes critical. Row Hammer (RH) is one of the reliability issues in sub-20 nm DRAM product. This work proposes an air gap technique [i.e., placing an air gap beneath passing wordline (PWL)], to suppress the RH in sub-20 nm DRAM. Using 3D TCAD simulations, the electric field and Shockley-Read-Hall (SRH) recombination rate are investigated when the PWL is activated. And, when the PWL is deactivated, the leakage current toward the bitline is extracted, to investigate the impact of the air gap on RH. It turned out that a low-k dielectric material in the air gap can effectively help to reduce the electric field intensity near the interface between shallow-trench-isolation (STI) and silicon. The relatively weak electric field can prevent the flow of electrons that causes read/write errors through trap-assisted recombination. By adopting the air gap in STI, 82 % improvement was estimated in terms of alleviating RH.

Next-Generation Low-k Dielectric Materials Required for Post-5G and 6G

Next-Generation Low-k Dielectric Materials Required for Post-5G and 6G

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

Computational Analysis of the Effects of Nanoscale Confinement on the Structure of Low-k Dielectric Hybrid Organosilicate Materials

Computational Analysis of the Effects of Nanoscale Confinement on the Structure of Low-k Dielectric Hybrid Organosilicate Materials

Fluoride- and Seed-Free Synthesis of Pure-Silica Zeolite Adsorbent and Matrix Using OSDA-Mismatch Approach.

The pure-silica zeolite plays a crucially important role in the gas separation of alkane/alkene, the low-k dielectric material, and the robust matrix for confining metal species during catalysis. However, the environmentally friendly synthesis of pure-silica zeolites is still challenging since (1) the toxic fluoride or dealuminum seeds are inevitably utilized through the hydrothermal synthesis and (2) it will also take a longer crystallization time. Herein, we present an efficient method called the OSDA-mismatch approach for the fluoride- and seed-free synthesis of pure-silica zeolites using Si-SOD (enriched 4-rings) as the sole silica source. This approach allows for the rapid and green synthesis of 15 pure-silica zeolites (CHA, *BEA, EUO, SFF, STF, -SVR, *-SVY, DOH, MTN, NON, *MRE, MEL, MFI, MTW, and *STO). Furthermore, distinct crystallization mechanisms of two significant pure-silica CHA- and *BEA-type zeolites (denoted as Si-CHA and Si-BEA) are investigated in detail by advanced characterization techniques such as FIB, 3D ED, 4D-STEM, HRTEM, Raman, and 29Si MAS NMR. More importantly, Si-CHA displays promising propane/propylene separation performance even better than the one synthesized in the presence of toxic HF. In addition, the incorporation of Zn species within Si-BEA fabricated by this approach also renders superior performance on propane dehydrogenation.

Investigating the degradation mechanisms of moisture on the reliability of integrated low-k stack

This study investigates the phenomenon of moisture diffusion within integrated circuits, focusing on low-k and SiCN dielectric materials. The research confirms the main pathway of moisture diffusion occurring through interfaces between materials. The various steps involved in the moisture diffusion mechanism are identified and linked to electrical characterizations, including variations in capacitance, modifications in leakage current behavior, and dielectric breakdown. A modification in the conduction mechanism is observed. The investigation also highlights different types of bonds formed between the dielectrics and moisture based on literature review and baking process. Saturated samples exhibit a partial reversibility after a 250 °C bake but do not fully recover. Nevertheless, reversibility is shown to be dependent on the moisture content reached prior to baking.

NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance

NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance. In particular, we use the well-known BSIM-CMG core solver for multigate transistors as a starting point and develop an ad hoc resistive and capacitive network to model the NS-GAAFET geometrical and physical structure. Then, we employ the developed model to design and optimize a digital inverter and a five-stage ring oscillator, which we use as a performance benchmark for the NS-GAAFET technology. Through Cadence Virtuoso SPICE simulations, we investigate the digital NS-GAAFET performance for both high-performance and low-power nodes, according to the average future node present in the International Roadmap for Devices and Systems. We focus our analysis on the main different technological parameters with regard to FinFET, i.e., the inner and outer spacers. Our results highlight that in future technological nodes, the choice of alternative low-K dielectric materials for the NS spacers will assume increasing importance, being as relevant, or even more relevant, than photolithographic alignment and resolution at the sub-nm scale.

Tröger’s Base (TB)-Based Polyimides as Promising Heat-Insulating and Low-K Dielectric Materials

The correlations between the molecular structures of four Tröger’s base (TB)-based polyimides (PIs) and two non-TB containing analogues and physical properties including thermal conductivity (λ) and dielectric properties both at low and high frequencies were investigated in detail. The TB-based PI films exhibited low dielectric constants (Dk = 2.25–2.80) at 10 GHz. They possessed much lower λ values (0.035–0.145 W/mK) compared to the commercial PI Kapton (0.240 W/mK). The influences of incorporating TB units into chain backbones on aggregation structures and physical properties of PIs were identified. Incorporating TB units into chain backbones effectively reduced the degree of chain orientation and increased fractional free volume, leading to both low Dk and low λ values for the resulting PI films. Also, introducing TB units enhanced molecular weights, toughness, and glass-transition temperature (Tg) of the resulting PIs. Therefore, the TB-based PIs can be promising heat-insulating and low-k dielectric materials.

Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses

With Copper (Cu) Interconnects causing performance bottleneck at single nanometer nodes due to increase in resistivity size effects viz., grain boundary scattering and surface scattering, there has always been scavenging for alternate interconnect materials. Although the Cu resistivity value decreases at cryogenic temperature, the problems continue to persist. In this work, we study three alternate interconnect materials specifically for 77K High Performance Compute applications. We select the materials based on their resistivity value at 77K for 7nm node computed using Fuchs-Sondheimer-Mayadas-Shatzkes (FS-MS) models. We analyze the delay of the interconnects, understand repeater insertion as a function of wire length, evaluate repeater count and energy at system level and perform IR drop analysis by showing through detailed analytical models that Ru, Rh and Al can provide appreciable improvements over Cu at 77K. The delay of interconnects reduces by 1-3.75% for Ru, 1.5-7.25% for Rh and 4.4-17.8% for Al across the BEOL stack while repeater counts decrease by 10%, 15% and 37% for Ru, Rh and Al respectively at 77K. We investigate thermal and reliability aspects of interconnect design including electromigration, Joule Heating and maximum allowed current densities again proving that Ru (9%), Rh (18%) and Al (63%) outperform Cu at 77K. Finally, we study the effects of various Low-k dielectric materials on the interconnect capacitance and thermal behavior for Cu as well as three alternate materials noting that, even though thermal conductivity of dielectrics decrease at 77K, the Joule Heating will not be as worse as one might expect.

(Invited) Computational Insights to Dielectric Hybrid Glasses Under Nanoscale Confinement for Next Generation Devices

Low and Ultra-k dielectric organosilicate glasses (OSG) are widely used in device interconnect applications such as shallow trench isolation as insulating units. However, the process of gap filling between conducting units has been challenging. One of the challenges is related to the undesired formation of nanovoids in the low-k dielectric material confined inside the trench geometry. Importantly, the effects of such nanoscale device constraints on the structure and mechanical reliability of low-k dielectric hybrid materials are not very well understood. To close this lack of understanding and guide the related experimental efforts we performed molecular dynamics simulations where we explore the role of the molecular structure and connectivity of different low-k dielectric OSG precursors under nanoscale confinement, and predict the resulting elastic and fracture properties. We demonstrated that hyperconnected OSG precursors with aromatic rings, such as the 1,3,5-benzene molecule, pack more homogenously under confinement leading to smaller nanovoids and better mechanical reliability compared to conventionally bridged OSG precursors, such as the ethylene bridged Et-OCS molecule.

Polymer Concentration and Liquid-Liquid Demixing Time Correlation with Porous Structure of Low Dielectric Polyimide in Diffusion-Driven Phase Separation.

Porous polyimide (PI) films are a promising low-k dielectric material for high-frequency data transmission with low signal attenuation. Pores are generated by non-solvent induced phase separation (NIPS) during phase inversion of polymer solution via non-solvent accumulation and solvent diffusion. In this study, aromatic PI was employed as a matrix for NIPS, and the influence of polymer concentration and liquid—liquid demixing time on the morphology of pores in the PI films was investigated. This ensured control over the porous structure of the PI film and provided desirable dielectric properties in a broad frequency range of 100 Hz–30 MHz (1.99 at 30 MHz) and thermal stability (Td5% > 576 °C, Tg > 391 °C). This study addresses the effect of polymer concentration and coagulation time on the morphology and physical properties of PI sponge films and provides guidance on the design and optimization of architectures for polymeric materials requiring pore modification.

Large Thermal Expansion LTCC System for Cofiring with Integrated Functional Ceramics Layers.

We have studied the sintering behavior of CT708 LTCC tapes with large CTE of 10.6 ppm/K. This low-k dielectric LTCC material is a quartz-based glass ceramic composite system with partial crystallization of celsian upon firing. The shrinkage, densification and dielectric properties were examined using different heating rates and a sintering temperature of 900 °C. The maximum shrinkage rate is at 836 °C (for a heating rate of 2 K/min) with a sintering density of 95% and a permittivity of ε’ = 5.9 and tan δ = 0.0004 (at 1 GHz). Due to their similar shrinkage and thermal expansion properties, CT708 tapes may be cofired with functional ceramic layers. As an example, we report on cofiring of a multilayer laminate of CT708 and a Sc-substituted hexagonal ferrite for applications as integrated microwave circulator components. This demonstrates the feasibility of cofiring of functional ceramic tapes and tailored LTCC tapes and documents the potential for the realization of complex LTCC multilayer architectures.

Reliability Characterization of a Low-k Dielectric Using Magnetoresistance as a Diagnostic Tool

Device reliability predictions of the low-k amorphous dielectric material SiCOH using its negative magnetoresistance (MR) is demonstrated herein. The magnitude of the MR is related to the density of defects at the interface and within the bulk of the dielectric material. Moreover, the mean-free path of carriers in the bulk dielectric material within the conduction band is increased in the presence of an applied external magnetic field due to the electron spin-polarization relaxation time modification cooperative effect resulting in suppression of the formation of singlet states and trap-mediated spin-singlet state pair hopping due to carrier spin constraints supporting triplet states with a concomitant rise in current in the conduction band. Interelectrode charge carrier conduction due to trap states within the bulk of the material leading to dielectric breakdown is a major detractor in insulators. A direct correlation is shown between the MR in the amorphous dielectric material SiCOH (a-SiCOH) and failure rates of the insulator in time-dependent dielectric breakdown (TDDB) material lifetimes.

The Evolution of Organosilicon Precursors for Low-k Interlayer Dielectric Fabrication Driven by Integration Challenges.

Since the application of silicon materials in electronic devices in the 1950s, microprocessors are continuously getting smaller, faster, smarter, and larger in data storage capacity. One important factor that makes progress possible is decreasing the dielectric constant of the insulating layer within the integrated circuit (IC). Nevertheless, the evolution of interlayer dielectrics (ILDs) is not driven by a single factor. At first, the objective was to reduce the dielectric constant (k). Reduction of the dielectric constant of a material can be accomplished by selecting chemical bonds with low polarizability and introducing porosity. Moving from silicon dioxide, silsesquioxane-based materials, and silica-based materials to porous silica materials, the industry has been able to reduce the ILDs’ dielectric constant from 4.5 to as low as 1.5. However, porous ILDs are mechanically weak, thermally unstable, and poorly compatible with other materials, which gives them the tendency to absorb chemicals, moisture, etc. All these features create many challenges for the integration of IC during the dual-damascene process, with plasma-induced damage (PID) being the most devastating one. Since the discovery of porous materials, the industry has shifted its focus from decreasing ILDs’ dielectric constant to overcoming these integration challenges. More supplementary precursors (such as Si–C–Si structured compounds), deposition processes (such as NH3 plasma treatment), and post porosity plasma protection treatment (P4) were invented to solve integration-related challenges. Herein, we present the evolution of interlayer dielectric materials driven by the following three aspects, classification of dielectric materials, deposition methods, and key issues encountered and solved during the integration phase. We aim to provide a brief overview of the development of low-k dielectric materials over the past few decades.

Magnetoresistance Recovery in the Amorphous Dielectric Material SiCOH

The use of a magnetoresistance in the characterization of transport properties in the amorphous low-k dielectric material SiCOH is demonstrated. The double occupancy of charge carriers in trap states within the dielectric material can only exist in spin singlet formation due to Pauli Exclusion. The trap-assisted negative magnetoresistance (MR) in amorphous SiCOH, driven by an applied electric field that results in an observed increase in magnitude of the current in the conduction band is due to singly occupied trap spin-mixing suppression of carriers with the application of an external magnetic field. The material MR decays with time under electrical bias and temperature stress as traps are filled by charge carriers and from space charge accumulation. The MR can be reinstated by the ionization of these traps via the conduction mechanisms of nonthermally activated tunneling and thermal ionization with the assistance of an applied coulombic potential barrier lowering electric field. In this work a direct correlation is shown between a material MR and the trapping, de-trapping, and trap avoidance of singly occupied traps in the transport of charge carriers in the amorphous low-k dielectric material SiCOH (a-SiCOH).

Introduction of Laser Pi-Grooving as Breakthrough Solution to Enhance die Strength of 40 nm ulow-k CMOS Silicon Technology during Wafer Saw Process

Nowadays, semiconductors and electronics are becoming part of our everyday activities. As the Integrated circuits become more useful to people, it also requires more function, which contain more complex and compact components. Aligned to this package requirement, the more challenging it become to package development as Silicon technology becomes more critical and complex from bare silicon to conventional MOS technology to Ultra Low-K, which requires a different strategy. The new process development in the Semiconductor industry is a necessity to cope up with these new technologies. Low-k devices always pose a big challenge in achieving good dicing quality. This is because of the weak mechanical properties of the low-k dielectric material used. Mechanical Sawing is the most popular cutting method for silicon, but with Ultra low-K technology, using mechanical sawing will lead to various sawing defects such as chippings and delamination [1,2]. These leads to the introduction of Laser Grooving to get rid of these dilemmas. Laser grooving uses heat to eradicate metals on this very thin metal wafer dicing saw streets in preparation for wafer saw process to prevent topside chippings and delamination/metal peel off [3]. These defects are not acceptable especially since the product application is a chip card. Since chip cards must be flexible and durable, they require higher die and package strength to serve its purpose. To achieve such package requirement, different method was evaluated such as standard mechanical dicing, standard Laser Grooving and the PI laser groove. 
 The paper will discuss how we were able to achieve the quality requirement for Ultra Low-K and at the same time eliminating top reject contributor during startup of this device.

Investigation of Fluoro-Carbon Layer on Dense Sicoh Formed during CF4 and CF4/C4F6 Based Continuous Wave Plasma Etch

Motivation: Plasma etching of low-k and ultra low-k (ULK) dielectric materials have seen a tremendous growth in deep nanoscale applications. Fluorocarbon based gases are the forerunners in etching low-k dielectrics as they are the F suppliers necessary to remove Si and C from SiCOH material. Different FC gases in combination with the additive gases contribute differently to the etch behavior of SiCOH due to differing reaction chemistry and formation of Fluorocarbon layer as an interfacial layer between plasma front and dielectric front [i]. Due to dynamic formation and etching of FC Layer happening at the dielectric surface, understanding FC layer properties in each gas plasma is the starting step to control etch rate and plasma induced damage in Low-k dielectrics. This paper aims to study and compare FC layer deposition by different gases grouped into CF4 and CF4/C4F6 family with N2, O2 and H2 as additive gases in each group. FC layer thickness, etch rate, optical properties of etched SiCOH and chemical composition of the FC layer by different plasma treatments have been presented in this work. Methodology: Dense SiCOH (k=2.75 and Open Porosity: 7%) with initial thickness of 157±3nm is deposited on 300mm Si Wafer with a thin SiO2 adhesion layer in between. These wafers are blanket etched in a commercial etch chamber with the given gas combinations (CF4, CF4/N2, CF4/O2, CF4/H2; CF4/C4F6, CF4/C4F6/N2, CF4/C4F6/O2, CF4/C4F6/H2) for same amount of time, total gas flow rate, similar power, pressure and temperature settings.Post Etch blanket wafers are subjected to various in-line and off-line metrology tools. In-line spectroscopic ellipsometer is used to model complex refractive index and thickness of individual layers. Tauc-Lorentz model best describes the FC layer whereas Cauchy model describes the dielectric [ii]. In-line XPS was carried out to probe the surface of FC layer and gain chemical information. Furthermore depth profile of etched layer is carried out by sputtering the surface with low power Ar ions to study variations in chemical composition with the layer depth. SEM is used to see the cross section profile and verify the results from above method Observation: Thickness evaluation from the dispersion models shows that the CF4 group has higher etch rate and lower FC layer thickness compared to CF4/C4F6 group. C4F6 has higher polymerization ability by the virtue of its lower F/C ratio. Amongst each group, Oxygen as additive gas shows the highest etch rate and least FC thickness followed by Nitrogen whereas Hydrogen has least etch rate but highest FC layer thickness. Under given etch conditions with CF4/C4F6/H2 plasma, deposition rate was higher than etching rate leading to stack growth (Fig.1a). Hydrogen supports polymerization by scavenging Fluorine away and aids in thicker FC films.XPS chemical composition shows Fluorine diffusion through FC layer into the dielectric layer bringing changes to its pristine structure. This affects Carbon% across the etched dielectric thickness (Fig.1b). Thicker the FC layer is, closer is the Carbon % to pristine SiCOH. Presence of surficial Nitrogen in the nitrogen containing plasmas shows nitrogen reacts with SiCOH Carbon, forms CN compounds and increases the etch rate. FC layer shows presence of CF3 radicals on the surface and decrease fast with the depth, followed by CF2 radicals. CF radicals are in larger quantity and are present deepest into the FC Layer. Presence of polymerized C-C and C-CFx bonds increases with the FC Layer depth and offset with increase of C-Si bond near the SiCOH interface. Conclusion: This paper shows comparison of Etch Rate and FC layer thickness during SiCOH etch using different gas combinations in the CCP plasma chamber. Thickness correlation between ellipsometric model data and XPS depth profile followed by SEM cross section measurement of layer thickness point towards the correctness of dispersion models for each layer. These models can be used for quick inline post etch metrology useful for process control. O2 containing plasmas are too aggressive on the dielectric with negligible FC layer formation, while H2 containing plasmas are less damaging but exhibit very small etch rate. CF4/C4F6/N2 plasma is the optimum combination for Low-k dielectric etch amongst other combinations in terms of desired etch rate and lower reduction in Carbon %. Relative concentration and penetration depth of different CFx radicals in FC film suggests its influence on film structure.

(Invited) Scaling of Copper Interconnection As Opposed to Alternative Conductors

Cu/low-k interconnection is facing to challenges in its extension per scaling in the 3nm node and beyond where the metal pitch is less than 32 nm. As is listed in Table.1, the difficulties lie in securing (1) Cu gap fill capability in scaled via in the dual damascene process flow due to the limited step coverage of PVD Cu seed layer, (2) Vx-Mx breakdown voltage and TDDB reliability due to scaled spacing and misalignment in lithography, (3) Electromigration reliability when the barrier/liner is scaled, (4) Low line resistance due to decreased Cu volume when the barrier/liner scaling is limited, (5) Low via resistance when the barrier/liner scaling is limited, (6) Selectivity in selective CVD deposition of cobalt capping layer which is required for electromigration reliability and (7) Low interconnect parasitic capacitance when thickness of the plasma-induced damage of the intra-layer low-k dielectric becomes comparable to the inter-metal spacing per scaling.Because of these difficulties in extension of dual damascene Cu interconnection scheme, various alternative metallization unit processes, materials (conductors and dielectrics) and schemes (alternative to dual damascene) have been investigated. These new processes and materials include both (a) those for extension of Cu technology such as Co_Cu hybrid metallization (i.e., Co for via and Cu for wires) and (b) those for entire replacement of Cu to other conductors. Basically extension of Cu interconnects is the preference in the industry rather than entire replacement to alternative conductors and/or metallization schemes, because entire replacement needs to be accompanied with alignment of all unit processes to the new metal schemes such as CMP and/or RIE of the new conductor, deposition of the conductor, wet cleaning compatible to the conductor, and nucleation/adhesion layer formation for the conductor on dielectrics, in all fine dimensions. In addition, even when fine Cu lines are replaced to alternative conductors such as Co, wide power rails need to stay with Cu for the required low line resistance (i.e., Cu_Co composite metallization).In this talk, process candidates which have potential to resolve the difficulties listed in Table 1 and enable extension of Cu interconnection scheme are reviewed such as (i) via pre-fill processes with vertical ALD of low-k dielectrics [1], (ii) plasma damage resistant low-k dielectric materials [2], (iii) Fully Aligned Via integration process [3], (iv) PVD-assisted ALD barrier formation [4, 5], (v) through cobalt self-forming barrier process barrier/liner scaling processes without loss in their integrity [1, 6 - 8], (vi) graphene capping material on top of Cu interconnects for electromigration reliability 10]. Then, the talk covers (vii) the composite metallization scheme [11] which is an enabler for the post-Cu alternative conductor metallization. Figure 1

Characterization of silane based ultra-thin barrier deposited at elevated temperature

In this work, we describe a quick turn-around characterization approach of ultra-thin layers on low dielectric constant (Low-K) interlevel dielectric using Electrochemical Impedance Spectroscopy (EIS). It is demonstrated on an organo-silane based ultra-thin Cu barrier layer, deposited from liquid phase at elevated temperatures, 90 °C - 150 °C, using high flash temperature solvents: N-methyl-2-pyrrolydone (NMP, Tflash-point = 91 °C) or Ethylene glycol (EG, Tflash-point = 116 °C). Three Silane (Head group) based monomers; with three different tail groups (e.g. amine, aniline and methacrylate) were investigated; The elevated temperature deposition process allowed shorter deposition times (less than 15 min), compared to previous publications. Additionally, the high flash point solvents reduce the risk of spontaneous explosion or ignition. All three monomers yielded satisfactory barrier against copper transport, being tested for more than 10 h at temperature higher than 400 °C, on all substrates. The need for a quick turn-around and a simple way to determine the barrier presence, its thickness and its coverage, lead to explore the application of Electrochemical Impedance Spectroscopy (EIS). We demonstrate the capability of that method estimating thickness and coverage of such ultra-thin barriers deposited on relatively thick (~200 nm) Low-K dielectric materials. It was found that EIS below 10 Hz at negative wafer bias vs. the electrolyte reference, the impedance real part was affected by the ultra-thin layer on thick dielectric materials allowing to define an Effective Electrical Coverage (EEC) of the films on Low-K dielectric similar to what has already been defined on bare silicon. The EEC is a figure of merit and its relation to the actual surface coverage, and barrier properties, is briefly discussed.

Investigation of Hetero Buried Oxide and Gate Dielectric PNPN Tunnel Field Effect Transistors

This paper investigates a novel hetero dielectric buried oxide and gate dielectric based PNPN tunnel field effect transistor (HDB-HDG-PNPN-TFET) using 2-D simulation. The buried oxide (BOX) is formed by SiO2 below the channel and source, HfO2 beneath the drain region. The asymmetrical gate oxide is formed by high-k and low-k dielectric material on the source and drain side respectively. The asymmetrical gate oxide decreases the tunneling width at the drain-channel (JDC) and source-channel (JSC) junctions and improves ON-current (ION). The buried oxide above the degenerated P+ substrate determines the tunneling width at the JDC and minimizes the ambipolar current. The device simulations show a low OFF-current (IOFF) of 4.21× 10−17 A/μm, a greater ION of 4.12× 10−4 A/μm, average and point subthreshold swing (SS) of 29.12 mV/dec and 19.38 mV/dec respectively for HfO2− SiO2 gate oxide. The above-mentioned result enables the device to be opted for low power applications.