Investigation of Hetero Buried Oxide and Gate Dielectric PNPN Tunnel Field Effect Transistors

Abstract

This paper investigates a novel hetero dielectric buried oxide and gate dielectric based PNPN tunnel field effect transistor (HDB-HDG-PNPN-TFET) using 2-D simulation. The buried oxide (BOX) is formed by SiO2 below the channel and source, HfO2 beneath the drain region. The asymmetrical gate oxide is formed by high-k and low-k dielectric material on the source and drain side respectively. The asymmetrical gate oxide decreases the tunneling width at the drain-channel (JDC) and source-channel (JSC) junctions and improves ON-current (ION). The buried oxide above the degenerated P+ substrate determines the tunneling width at the JDC and minimizes the ambipolar current. The device simulations show a low OFF-current (IOFF) of 4.21× 10−17 A/μm, a greater ION of 4.12× 10−4 A/μm, average and point subthreshold swing (SS) of 29.12 mV/dec and 19.38 mV/dec respectively for HfO2− SiO2 gate oxide. The above-mentioned result enables the device to be opted for low power applications.