(Invited) Scaling of Copper Interconnection As Opposed to Alternative Conductors

Abstract

Cu/low-k interconnection is facing to challenges in its extension per scaling in the 3nm node and beyond where the metal pitch is less than 32 nm. As is listed in Table.1, the difficulties lie in securing (1) Cu gap fill capability in scaled via in the dual damascene process flow due to the limited step coverage of PVD Cu seed layer, (2) Vx-Mx breakdown voltage and TDDB reliability due to scaled spacing and misalignment in lithography, (3) Electromigration reliability when the barrier/liner is scaled, (4) Low line resistance due to decreased Cu volume when the barrier/liner scaling is limited, (5) Low via resistance when the barrier/liner scaling is limited, (6) Selectivity in selective CVD deposition of cobalt capping layer which is required for electromigration reliability and (7) Low interconnect parasitic capacitance when thickness of the plasma-induced damage of the intra-layer low-k dielectric becomes comparable to the inter-metal spacing per scaling.Because of these difficulties in extension of dual damascene Cu interconnection scheme, various alternative metallization unit processes, materials (conductors and dielectrics) and schemes (alternative to dual damascene) have been investigated. These new processes and materials include both (a) those for extension of Cu technology such as Co_Cu hybrid metallization (i.e., Co for via and Cu for wires) and (b) those for entire replacement of Cu to other conductors. Basically extension of Cu interconnects is the preference in the industry rather than entire replacement to alternative conductors and/or metallization schemes, because entire replacement needs to be accompanied with alignment of all unit processes to the new metal schemes such as CMP and/or RIE of the new conductor, deposition of the conductor, wet cleaning compatible to the conductor, and nucleation/adhesion layer formation for the conductor on dielectrics, in all fine dimensions. In addition, even when fine Cu lines are replaced to alternative conductors such as Co, wide power rails need to stay with Cu for the required low line resistance (i.e., Cu_Co composite metallization).In this talk, process candidates which have potential to resolve the difficulties listed in Table 1 and enable extension of Cu interconnection scheme are reviewed such as (i) via pre-fill processes with vertical ALD of low-k dielectrics [1], (ii) plasma damage resistant low-k dielectric materials [2], (iii) Fully Aligned Via integration process [3], (iv) PVD-assisted ALD barrier formation [4, 5], (v) through cobalt self-forming barrier process barrier/liner scaling processes without loss in their integrity [1, 6 - 8], (vi) graphene capping material on top of Cu interconnects for electromigration reliability 10]. Then, the talk covers (vii) the composite metallization scheme [11] which is an enabler for the post-Cu alternative conductor metallization. Figure 1