Low-k Dielectric Materials Research Articles

TCAD Simulation of the Doping-Less TFET with Ge/SiGe/Si Hetero-Junction and Hetero-Gate Dielectric for the Enhancement of Device Performance

The device structure of DLTFET is optimized by the Silvaco TCAD software to solve the problems of lower on-state current and larger miller capacitance of traditional doping-less tunneling field effect transistors (DLTFETs), and the performance can be greatly improved. Different from the traditional DLTFETs, the source region and pocket region of the doping-less TFET with the Ge/SiGe/Si hetero-junction and hetero-gate dielectric (H-DLTFET), respectively, use the narrow band-gap semiconductor Ge and SiGe materials, and the channel and drain region both use the silicon material. The H-DLTFET device use the Ge/SiGe hetero-junction engineering to decrease the tunneling barrier width, increase the band-to-band tunneling current, and obtain the higher current switching ratio and ultra-low sub-threshold swing (SS). Besides, the gate dielectric under auxiliary gate uses the low-k dielectric SiO2 material, which can effectively reduce the miller capacitance and improve the capacitance and frequency characteristics. The on-state current, switching ratio, trans-conductance, output current, and output conductance values of H-DLTFET can be increased by two, two, one, one, and one order of magnitude when compared with the DLTFET, respectively. Meanwhile, the point SS and average SS, respectively, decrease from 13 mV/Dec and 31.6 mV/Dec to 5 mV/Dec and 14.3 mV/Dec, and the gate-drain capacitance decrease from 0.99 fF/μm to 0.1 fF/μm. Besides, the cutoff frequency and gain bandwidth product of H-DLTFET are much larger than that of DLTFET, which can be explained by the excellent DC characteristics. The above simulation results show that the H-DLTFET has the better frequency characteristics, so it is more suitable for applications of ultra-low-power integrated circuits.

Plasma Induced Damage Reduction of Ultra Low-k Dielectric by Using Source Pulsed Plasma Etching for Next BEOL Interconnect Manufacturing

In order to reduce the interconnect resistance and capacitance (RC) time delay of a semiconductor integrated circuit, a more porous dielectric material is used in recent interconnection for lower dielectric constant. However, it is difficult to use highly porous low-k dielectric materials at the narrow pitch because it is easily damaged during the plasma etching processes. In this study, as one of the plasma induced damage reduction methods in the etching of porous low-k dielectric, RF pulsed plasma methods have been investigated by using a dual frequency capacitively coupled plasma etching system. RF pulsed plasmas generated more polymerizing species and less UV compared to continuous wave plasmas and showed reduced damaged layer compared to the conventional continuous wave plasma etching. Porous SiCOH dielectric patterned with a TiN hard mask was etched using the RF pulsed plasmas and the results showed more anisotropic etching profiles with less sidewall damages, which was estimated by the thickness loss of sidewall low-k material after dipping into a diluted HF solution. Therefore, it is believed that the RF pulsed plasma etching process of ultra low-k dielectric materials can improve the RC time delay related to plasma damage for the next interconnect manufacturing technology.

Novel Volatile Film for the Protection of Organo-Silicate Glass Dielectric Materials

In back-end-of-the-line (BEOL) patterning process, porous low-k dielectrics are degraded by plasma reactive species during etching and resist stripping –this is so-called plasma induced damage (PID). PID increases the k-value of dielectrics and inter-line capacitance, which causes resistive-capacitive (RC) delay. In this paper, the authors introduce two approaches to suppress the PID, using a novel volatile organic film. The first approach is an improved Post Porosity Plasma Protection (P4, or pore stuffing), and the second approach is based on the use of a temporary plug. In the case of pore stuffing, the filling ability and protection effect are evaluated on various blanket low-k dielectric materials. For the plug approach, its effectiveness is demonstrated in terms of electrical characteristics and reliability using a patterned interconnect test vehicle.

A Study on Reduced/Absent Adhesion/Cap Layers for Optimized BEOL RC Performance

Abstract Lower RC delay is vital to achieve optimal and competitive circuit performance and hence drives the endlessly pursued BEOL integration scheme advancement. To date low-k dielectric materials, i.e., fluorine-doped oxides, carbon-doped oxide (SiCOH), to porous carbon-doped oxides (p-SiCOH) have been implemented. However, due to the process integration challenges with inherently weak low-k materials, the trend to pursue lower k dielectrics has come to a plateau as technology nodes scale down past 20/14nm. On the other hand, the trend of geometry layer thickness shrinking down, such as trench CD and height, via CD and height, etc., still continues for each advanced technology node. In the BEOL stack adhesion layers (oxide + gradient layers) (ALs) with higher k value were introduced to enhance interface adhesion strength between SiCOH/p-SiCOH and dielectric cap film (SiCN), which offset the intrinsic RC benefit from low-k dielectric material. At more advanced nodes and beyond, the combined ALs and cap film could be up to via or trench height, which poses a huge challenge to meet desired RC performance and technology node scaling. Therefore, the thickness reduction of ALs and cap film becomes necessary for further technology node scaling. In this study, samples with interfacial full ALs, reduced ALs and bulk only (no ALs) for p-SiCOH (k=2.75) on various cap films were prepared, such as SiCN, SiCN/ODC, SiCN/AlONx, etc. TOF-SIMS analyses was used to confirm the composition of the dielectric stacks and later check the debonded surface morphology. Four-point bend adhesion tests were conducted to evaluate interfacial adhesion strength. Results show the interfacial adhesion strength on samples with reduced Als and bulk only (no ALs) is dropped by ~20% and ~30%, respectively. Additional ODC layer on top of SiCN would increase the interfacial adhesion strength by ~10%. It is suggested that reduced ALs may be adequate to satisfy overall CPI requirement for the BEOL integration scheme of p-SiCOH on advanced dielectric cap films (AlN + ODC). The coupling capacitance reduction for a combined reduced ALs and advanced dielectric cap can be up to 16% at M0 level and 10% at Mx level for a 40nm metal pitch.

Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

To improve the on-state current and reduce the miller capacitance of the conventional junction-less tunneling field effect transistor (JLTFET), the junction-less TFET with Ge/Si0.3Ge0.7/Si heterojunction and heterogeneous gate dielectric (H-JLTFET) is investigated by the Technology Computer Aided Design (TCAD) simulation in this paper. The source region uses the narrow bandgap semiconductor material germanium to obtain the higher on-state current; the gate dielectric adjacent to the drain region adopts the low-k dielectric material SiO2, which is considered to reduce the gate-to-drain capacitance effectively. Moreover, the gap region uses the Si0.3Ge0.7 material to decrease the tunneling distance. In addition, the effects of the device sizes, doping concentration and work function on the performance of the H-JLTFET are analyzed systematically. The optimal on-state current and switching ratio of the H-JLTFET can reach 6 µA/µm and 2.6 × 1012, which are one order of magnitude and four orders of magnitude larger than the conventional JLTFET, respectively. Meanwhile, the gate-to-drain capacitance, off-state current and power consumption of the H-JLTFET can be effectively suppressed, so it will have a great potential in future ultra-low power integrated circuit applications.

Etch Damage Reduction of Ultra Low-k Dielectric by Using Pulsed Plasmas

To reduce interconnect resistance and capacitance (RC) time delay of semiconductor integrated circuit, the dielectric material with more porosity is used in recent interconnection for lower dielectric constant. However, it is difficult to use highly porous low-k dielectric materials at the narrow pitch because it is easily damaged during the plasma etching processes. In this study, as one of the plasma induced damage reduction methods in the etching of porous low-k dielectric using C4F8-based gases, RF pulsed plasma methods have been investigated by using a dual frequency capacitively coupled plasma etch system. RF pulsed plasmas generated higher carbon-rich radicals in the plasma and less charging effect on the dielectric material surface compared to continuous wave plasmas and, therefore, showed a reduced damaged layer compared to the conventional continuous wave plasma etching. Porous SiCOH dielectric with a patterned TiN hard mask was etched using the RF pulsed plasmas and the results showed more anisotropic etching profiles with less sidewall damages. Therefore, it is believed that the RF pulsed plasma etching process of ultra low-k dielectric materials can improve the RC delay related with plasma damage for the next interconnect technology.

Self-Assembled Monolayers on Highly Porous Low-k Dielectrics by 3-Aminopropyltrimethoxysilane Treatment

Highly porous low-dielectric-constant (low-k) dielectric materials with a dielectric constant (k) less than 2.50 are needed for 32 nm and beyond technological nodes. In this study, a highly porous low-k dielectric film with a k value of 2.25, open porosity of 32.0%, and pore diameter of 1.15 nm were treated by 3-Aminopropyltrimethoxysilane (APTMS) in wet solution in order to form self-assembled monolayers (SAMs) onto it. The effects of the formation SAMs on the electrical characteristics and reliability of highly porous low-k dielectric films were characterized. As SAMs were formed onto the highly porous low-k dielectric film by APTMS treatment, the dielectric breakdown field and the failure time were significantly improved, but at the expense of the increases in the dielectric constant and leakage current. Moreover, the formation SAMs enhanced the Cu barrier performance for highly porous low-k dielectric films. Therefore, the SAMs derived from APTMS treatment are promising for highly porous low-k dielectric films to ensure better integrity.

Wet-chemical etching of metals for advanced semiconductor technology nodes: Ru etching in acidic Ce4+ solutions

The electrochemistry of ruthenium (Ru) etching in acidic solution containing cerium (IV) (Ce4+) has been investigated. Voltammograms were measured to determine the onset potentials of metal stripping and cathodic reduction of the oxidizing agent. Etch rates of blanket thin films of chemical vapour deposited Ru were measured using Rutherford backscattering spectrometry. Sheet resistance measurements of a thickness range of wet-chemically etched and as-deposited Ru thin films are compared. X-ray photoelectron spectroscopy was used to characterize post-etching residues. Using atomic force microscopy, the surface morphology of Ru after etching and removal of residues by rinsing with water or acid and ultrasonic agitation was studied. Compatibility of low-k dielectric material with the etchant has been assessed using Fourier transform infrared spectroscopy. UV–vis absorption spectroscopy was used to study the stability and absorption features of various Ce4+ compounds in sulphuric and methane sulphonic acid. Additionally, mixtures containing Ce4+ and Ce3+ were analyzed. In situ measurements during Ru etching show the conversion of the oxidizing agent to Ce3+.

Investigation of electrical and thermal property of poly(vinyl alcohol)–calcium titanate nanocomposites

The poly(vinyl alcohol):CaTiO3 nanocomposites were prepared by solution casting method using triethanolamine as a dispersive solvent in different weight percentages. The prepared nanocomposites have been characterized by FTIR and XRD for structural analysis. FTIR spectra show the important peaks of CaTiO3 and PVA which confirms the formation of nanocomposites. XRD pattern shows that the CaTiO3 has orthorhombic structure and its crystal structure does not distorted even after dispersion in PVA matrix. The TGA graph confirms that the addition of CaTiO3 (0.3 wt%) enhance the thermal stability of the nanocomposites. Further, the temperature dependent conductivity shows the increase in conductivity due to the tunnelling of charge carriers. Dielectric constant and dielectric loss of the 0.3 wt% of nanocomposites is low compare to other nanocomposites and hence its conductivity is high. It is found that the damping loss is 0.002% as indicated in quality factor and tangent loss is almost constant after 104 Hz which indicates that these nanocomposites can be used as low k-dielectric materials in electronic application.

Investigation on Electrical and Optical Properties of Hydrogen Doped Boron Carbide Thin Films

As complementary metal oxide semiconductor (CMOS) devices shrink to smaller size, the resistance-capacitance (RC) delay in metal interconnects remains critical bottleneck for improving performance. Search for new low-k dielectric materials to reduce the dielectric capacitance has been a priority for a long time. Boron carbide (B4C) has attracted interest as a material for low-k dielectric applications owing to its unique properties. In this work, thin films of boron carbide are deposited by RF magnetron sputtering in presence of hydrogen gas. Metal-insulator-metal structure using aluminum and boron carbide are formed. Herein, we investigate the dielectric properties (frequency dependent dielectric constant), electrical properties (resistivity) and optical properties (transmission) of hydrogen doped boron carbide thin films. Further, the effect of deposition parameters on properties of hydrogen doped boron carbide films is reviewed.

Future Dielectric Materials for CNT Interconnects - Possibilities and Challenges

Carbon nanotube (CNT) interconnects are emerging as the ultimate choice for next generation ultra large scale integrated (ULSI) circuits. Significant progress in precise growth of aligned CNTs and integration of multiwalled CNT interconnects into a test chip make them promising candidates for future nanoelectronic chips. Tremendous research efforts were made on silicon based ultra-low-k dielectrics for Cu interconnects, but, the most recent advancements in polymer based composites as dielectric materials open up fresh challenges in the use of low-k dielectrics for CNT interconnects. This paper reviews the emerging polymer composites like Boron Nitride Nanotubes, Graphene/Polyimide composites, Metal Organic Frameworks and small diameter CNTs. Many reviews are already exists on the synthesis, fabrication, dielectric, mechanical, chemical and thermal properties of these materials. In this review, we have explained the specific properties of these materials and the necessities for integrating them into CNT interconnects to meet the requirements of future IC designers.Keywords: low-k dielectric materials, ultra low-k dielectrics, carbon nanotubes, interconnects, dielectric constant,

Investigation on Electrical Properties of Hydrogen Doped Boron Carbide Thin Films

The ever-increasing advancements in semiconductor technology and continuous scaling of CMOS devices demands need for new low-k dielectric materials. Boron Carbide (B4C) has attracted recent attention due to its complicated crystalline structure and interesting properties. B4C is the third hardest material with a hardness > 30GPa after diamond and cubic boron nitride [1]. However, with increase in temperature, the hardness of diamond and cubic boron nitride decreases gradually. B4C is characterized to be the hardest material at even above 1100°C [2]. Other interesting properties exhibited by boron carbide are low specific weight, high modulus, high chemical stability and good wear resistance. These properties make boron carbide a promising material for applications in cutting tools. In this study, electrical properties of hydrogen doped boron carbide thin films will be investigated. Boron carbide films are deposited by magnetron RF sputtering of B4C target. Films are deposited at different temperatures in presence of hydrogen/argon gas to investigate the influence of temperature and hydrogen on electrical properties of boron carbide thin films.

Optical and Electrical Properties of ECR-PECVD Grown SiCN Thin Films

Recent progress in scaling down the metal-oxide semiconductor (MOS) devices accompanied limitations arising from quantum effects, which leads to a search for new materials. Silicon oxide (SiO2) thin films have been a favourable dielectric for more than 4 decades. Their usage have become impractical due to the power dissipation and delay in interconnects. To increase the electrical performance, low extinction coefficient (low-k) dielectric materials are being developed as a substitute to SiO2. Those materials draw considerable attraction due to their advances in the integrated circuit technology to increase the transistor density. Among numerous materials, silicon carbonitride (SiCN), which is an intermediate compound between silicon nitride (SiN) and silicon carbide (SiC), has become noteworthy with its unique properties as low-k, robustness, high thermal stability, and wide bandgap of 2.2eV- 5eV1. In this work we present the optical, structural, and electrical analysis of SiCN thin films grown using electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD). The influence of the precursors (SiH4, C2H2, and N2 gases) on the composition and electronic structure of thin films which were characterized by Rutherford backscattering spectroscopy (RBS) and Fourier transmission infrared spectroscopy (FTIR). Furthermore, current-voltage characteristics were studied in dark and illuminated environment at room temperature. We studied the variation of photodiode characteristics with the thin film compositions. These results were also compared with the SiCN thin films growth using identical parameters except for the carbon source (CH4 gas) which has been reported in earlier studies2. Our findings showed that the hydrogen content influenced the optical coefficients of these two set of samples. Index of refraction and extinction coefficients were characterized by variable angle spectroscopic ellipsometry (VASE). In addition to our works on developing low-k matrix to enhance the performance of the integrated circuits, the wide gap feature of SiCN thin films enable us to consider the ultraviolet (UV) photo responsivity effect which is studied for photodetector device application.

Physics-Based Compact TDDB Models for Low- $k$ BEOL Copper Interconnects With Time-Varying Voltage Stressing

Time-dependent dielectric breakdown (TDDB) is one of the important failure mechanisms for copper (Cu) interconnects. This problem becomes more severe as the pitch between wires is shrinking and low-k dielectric materials (low electrical and mechanical strength) are used. Many TDDB models have been proposed based on different physics kinetics in the past. Recently, a physics-based TDDB model, which is based on the breakdown concept of electric path generation, has been proposed and has shown advantage over widely accepted existing electrostatic field-based TDDB assessment. However, determination of the time-to-failure from this model includes time-consuming finite-element method (FEM). In this paper, we try to mitigate this problem by developing fast time to failure evaluation method based on the closed form solution of the ion diffusion partial differential equations. We show that the location of the minimum concentration can be determined by the dominant terms with sufficient accuracy and the time to failure can also be computed with a few dominant terms. On top of this, we also consider the time-varying stressing voltages, which is commonly seen in practical VLSI chips. We propose to develop the equivalent dc stressing voltage, which is parameterized in terms of amplitude, duty cycle, and period for periodic stressing voltage waveforms using regression-based method. We further validate the proposed analytic TDDB concentration and time to failure formula, and the equivalent dc stressing voltage compact model against the results of an FEM analysis using COMSOL. Numerical results further show that the new compact TDDB model can lead to three orders of magnitude speedup with less than 1% error against the existing FEM results.

Engineering of optical and electronic band gaps in transition metal dichalcogenide monolayers through external dielectric screening

In order to fully exploit the potential of transition metal dichalcogenide monolayers (TMD-MLs), the well-controlled creation of atomically sharp lateral heterojunctions within these materials is highly desirable. A promising approach to create such heterojunctions is the local modulation of the electronic structure of an intrinsic TMD-ML via dielectric screening induced by its surrounding materials. For the realization of this non-invasive approach, an in-depth understanding of such dielectric effects is required. We report on the modulations of excitonic transitions in TMD-MLs through the effect of dielectric environments including low-k and high-k dielectric materials. We present absolute tuning ranges as large as 37 meV for the optical band gaps of WSe 2 and MoSe 2 MLs and relative tuning ranges on the order of 30% for the binding energies of neutral excitons in WSe 2 MLs. The findings suggest the possibility to reduce the electronic band gap of WSe 2 MLs by 120 meV, paving the way towards dielectrically defined lateral heterojunctions.

On the use of (3-trimethoxysilylpropyl)diethylenetriamine self-assembled monolayers as seed layers for the growth of Mn based copper diffusion barrier layers

In this work x-ray photoelectron spectroscopy is used to investigate in-vacuo, the interaction of metallic manganese with a (3-trimethoxysilylpropyl)diethylenetriamine (DETA) self-assembled monolayer (SAM) on SiO2 and non-porous low-k dielectric materials. Subsequent deposition of a ∼0.5nm thick Mn, followed by a 200°C anneal results in the Mn diffusing through the SAM to interact with the underlying SiO2 layer to form a Mn-silicate layer. Furthermore, there is evidence that the Mn interacts with the carbon and nitrogen within the SAM to form Mn-carbide and Mn-nitride, respectively. When deposited on low-k materials the Mn is found to diffuse through to the SAM on deposition and interact both with the SAM and the underlying substrate in a similar fashion.

Nano-Architected 3D Ultra Low-k Dielectrics

Low-k dielectric materials have become increasingly critical to the semiconductor industry as the interconnect delay becomes an overwhelming portion of the total device signal delay. Many attempts at lowering the dielectric constant involve using organic materials or introducing stochastic porosity; these solutions often lack the mechanical resilience that is necessary for devices to survive in-use operation and introduce challenges for integration within traditional semiconductor processing. We demonstrate the fabrication of a 3-dimensional nano-architected low-k dielectric material that is comprised of hollow alumina tubes and contains 99% air. It has a stiffness of 30MPa and a dielectric constant well within the ultra low-k regime (below 2.0). We utilized two-photon lithography direct laser writing followed by atomic layer deposition to create these architectures. In addition to the low dielectric constant and high mechanical stiffness, these structural meta-materials exhibit exceptional energy absorption when uniaxially compressed and favorable electrical breakdown properties.

Boron and high-k dielectrics: Possible fourth etch stop colors for multipattern optical lithography processing

In a companion article, the etch characteristics of materials within the Si-C-O-N-H system were surveyed using two common fluorinated plasma etches used to etch SiO2 interlayer dielectrics and SiN:H etch stop layers (CHF3 and CF4/O2, respectively) with the goal of identifying new materials or “colors” to assist in the simplification of advanced multipass optical lithography. In this study, the authors investigate additional materials outside the traditional Si-C-O-N-H phase diagram with the hope of identifying potential third or fourth color pattern-assist materials. The specific materials investigated include a series of high-k dielectrics commonly used in the industry (Al2O3, AlN, and HfO2) and boron-based solids (a-B:H, a-BxN:H, a-BxP:H, and a-BxC:H) that have been previously identified as potential hard mask, polish stop, and/or low-k dielectric materials. The high-k dielectrics were all found to exhibit low to unmeasureable etch rates in both fluorinated etches. In contrast, the boron-based solids all exhibited etch rates in the CF4/O2 etch up to an order of magnitude or more higher than those of silicon-based materials while still exhibiting comparable etch rates in the CHF3 interlayer dielectric etch. The high-k dielectrics thus appear to be potential third or fourth color materials, provided etch chemistries capable of selectively etching these relative to other silicon- and carbon-based materials can be identified. The results for the boron-based solids suggest more immediate applications in patterning silicon-based materials. A more detailed examination of the B-C-H system also suggests that significant optimization of the etch selectivity can be achieved via compositional tuning for a-BxC:H and other boron-based dielectric materials.

Negative thermal coefficient behaviour, dielectric and mechanical properties of poly(vinyl chloride)/poly(vinyl alcohol) blends

Abstract Polyvinyl alcohol (PVA) in polyvinyl chloride (PVC) blends were prepared by using extrusion molding technique in various weight percentages. The prepared blends were characterized by FTIR and SEM for structural and surface morphology study. Further, the DC conductivity was studied by two probe method and found that the 6% of PVC–PVA blends shows high conductivity of 8.34×10 −7 S cm −1 . This increase in conductivity may be due to the extended chain length of blends, which is confirmed by the negative thermal coefficient graphs. The AC conductivity of blends increases with increase in applied frequency. Among all blends, 6 wt % shows high conductivity of 2.59×10 −6 S cm −1 and low tangent loss of 0.9 Ω. The PVC with PVA blends enhances the mechanical strength and modulus property as the percentage of elongation increases up to ~660, hence these polymer blends can be used in many applications like solar cells and gas sensor encapsulation device, low k-dielectric materials, food packing and other electronic devices.

Evaluation of Post Etch Residue Cleaning Solutions for the Removal of TiN Hardmask after Dry Etch of Low-k Dielectric Materials on 45 nm Pitch Interconnects

In the BEOL, as interconnect dimensions shrink and novel materials are used, it has become increasingly difficult for traditional PERR removal chemicals to meet the evolving material compatibility requirements. As a result, formulated cleans that specifically target these unique challenges are required. Two formulated BEOL cleans were evaluated on blanket and patterned wafer coupons for their ability to wet etch titanium nitride (TiN) and clean post-plasma etch residue, while remaining compatible to interconnect metals (Cu and W) and low-k dielectric (k = 2.4). Both, showed an improvement in material compatibility relative to dilute HF, while simultaneously being able to remove the TiN hardmask and post-etch residue, leading > 90% yield on test structures of varying sizes.