Low Junction Leakage Research Articles

Wet chemical poly-Si(n) wrap-around removal for TOPCon solar cells

This work gives an overview on different technological solutions for polysilicon removal in industrial tunnel oxide passivated contact (i-TOPCon) n-type silicon solar cell fabrication. The removal of parasitically deposited poly-Si layers on the front and the edges is a mandatory requirement for a low reverse bias junction leakage current (Irev). A polysilicon removal study on wafer level shows (i) that the efficient removal of the surface oxide layer before poly-Si etching is crucial to achieve short etching times and (ii) that an additive in the KOH solution enhances etching selectivity between poly-Si and silicon oxide surfaces. To evaluate the impact on device level, TOPCon cells have been fabricated in parallel using in-situ n-doped PECVD and LPCVD layers, as well as ex-situ LPCVD poly-Si layers, with another variation of poly-Si removal processes, namely wet chemical inline, wet chemical batch cluster and atmospheric dry etching (ADE). Our results show that a two-minute inline polysilicon removal in hot KOH meets the Irev qualification in case of as deposited in-situ doped layers, whereas for ex-situ doped layers a batch process with a five-minute KOH etching time is needed. LPCVD poly-Si cells show efficiencies above 23%, PECVD poly-Si cells with a batch cluster poly-Si removal process up to 23.4%.

Study on the cleaning process of n+-poly-Si wraparound removal of TOPCon solar cells

The use of tunnel oxide passivated contact (TOPCon) solar cells on the n-type Cz-Si wafers has thus far attracted more interest in the photovoltaics (PV) industry. However, the cells encounter the problems of wraparound appearance and edge leakage current. These phenomena can result in the decrease in the optical and electrical performance of the cells, such as open circuit voltage (Voc), short-circuit current density (Jsc), and fill factor (FF). In this work, several cleaning processes were adopted to resolve the problems for cells. The wraparound model and experimental results indicated that an effective cleaning process was carried out and revealed the correlation between the removal of the wraparound film and the edge junction layer on the surface of wafers. The optimized cleaning process did not destroy the boron-doping layer on the front side, and the poly-Si layer on the rear side. This process combined an inline etching process of HF/HNO3 treatment and a batch-type etching process of the KOH/polish additives solution treatment, which could effectively solve the problems associated with optical properties and achieve a low reversed-biased junction leakage current (IRev) 0.15 A at −14.5 V. After optimization of the rear surface recombination and the boron diffusion processes, industrial-type TOPCon cells at the present pilot line were obtained with the efficiency (Eff), Voc, Jsc and FF of 23.53%, 706 mV, 40.65 mA/cm2 and 82.02%, respectively. This optimized cleaning process could be applied and promoted in the PV industry.

Well-behaved Ge n+/p shallow junction achieved by plasma immersion ion implantation

Ge n+/p junctions fabricated by conventional ion implantation (CII) and plasma immersion ion implantation (PIII) are compared in this work. To achieve low junction leakage current, PIII-implanted Ge n+/p junctions require higher annealing temperature to eliminate the Shockley-Read-Hall generation current, which may be contributed to the residual hydrogen and hydrogen-related defects. It is demonstrated that with 500 °C annealing, well-behaved Ge n+/p junction with ultra-shallow junction depth (<50 nm) can be achieved by PIII. With 600 °C annealing, best Ge n+/p junction performance with current on/off ratio ~9 × 105 and ideality factor ~1.07 is achieved by PIII.

Impact of Punch-through Stop Implants on Channel Doping and Junction Leakage for Ge &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${p}$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-FinFET Applications

Fin field-effect transistor (FinFET) scaling beyond the 10-nm node requires formation of a junction isolation region between the source and the drain to suppress sub-fin leakage current. In this paper, heavy species such as Sb and As were implanted at room temperature to form a punch-through stop (PTS) layer in n-Ge substrates. The impact of PTS implants on channel doping and defects, as well as junction leakage, was investigated for bulk Ge p-FinFET applications. We report retrograde doping profiles with a low surface (channel) dopant concentration of 4-5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> for Sb PTS implants post 550 °C and 650 °C activation anneals. Besides achieving low effective channel doping, the 650 °C high-temperature activation anneal post PTS implant also helps in the reduction of channel defect density. Furthermore, low junction leakage currents are also demonstrated for Sb and As PTS implants with 550 °C and 650 °C activation anneals. To avoid damaging the FinFET channel layer due to PTS ion implantation, Ge homoepitaxy was also studied post Sb PTS implants. However, Sb PTS implants activated at 650 °C without Ge epitaxy exhibit the best results in terms of low channel dopant and defect concentrations, besides junction leakage.

Effect of Millisecond Annealing Temperature of Ni1-&lt;italic&gt;x&lt;/italic&gt;Pt&lt;italic&gt;x&lt;/italic&gt; Si Formation on Leakage Current Characteristics of Static Random- Access Memory Cells

The importance of optimizing the millisecond annealing (MSA) temperature for Pt-doped NiSi ( ${\mathrm {Ni}}_{{1}-{x}}$ Pt x Si) contact formation was highlighted by implementing and characterizing the ${\mathrm {Ni}}_{{1}-{x}}$ Pt x Si films in the static random-access memory (SRAM) cells fabricated with a 28-nm design rule. MSA at 750 °C–900 °C effectively reduced the junction leakage current compared to that with the conventional rapid thermal annealing, because of its efficient suppression of Ni diffusion in the junction region. Moreover, with an increase in the MSA temperature, the beneficial effects of maintaining a low junction leakage, such as interface flattening and grain size increase, were observed. However, the increase in the MSA temperature deteriorated the statistical distribution of the standby leakage current of the SRAM cells by producing more encroachment and spiking defects; this was attributed to the build-up of a high initial film stress and large stress relaxation during the subsequent back-end processes.

Performance enhancement of Ge-on-Insulator tunneling FETs with source junctions formed by low-energy BF2 ion implantation

To clarify the process of formation of source regions of high-performance Ge n-channel tunneling field-effect transistors (TFETs), p+–n junctions formed by low-energy ion implantation (I/I) of BF2 atoms are characterized. Here, the formation of p+–n junctions with steep B profiles and low junction leakage is a key issue. The steepness of 5.7 nm/dec in profiles of B implanted into Ge is obtained for BF2 I/I at 3 keV with a dose of 4 × 1014 cm−2. Ge-on-insulator (GOI) n-TFETs with the source tunnel junctions formed by low-energy B and BF2 I/I are fabricated on GOI substrates and the device operation is confirmed. Although the performance at room temperature is significantly degraded by the source junction leakage current, an Ion/Ioff ratio of 105 and the minimum sub-threshold swing (S.S.) of 130 mV/dec are obtained at 10 K. It is found that GOI n-TFETs with steeper B profiles formed by BF2 I/I have led to higher on current and a lower sub-threshold slope, demonstrating the effectiveness of steep B profiles in enhancing the GOI TFET performance.

(Invited) Smartphones: Driving Technology to More than Moore 3-D Stacked Devices/Chips and More Moore FinFET 3-D Doping with High Mobility Channel Materials from 20/22nm Production to 5/7nm Exploratory Research

Today smartphone ICs are driving technology to More Moore 3-D device scaling and More Than Moore 3-D stacked devices with >1.24B smartphones sold in 2014 accounting for >27% of all ICs. The expected increase in smartphone application processor (AP) demand in 2015 (Samsung Exynos 7 for Galaxy S6 and Apple A9 for iPhone 6s/7) is driving the rapid ramp to 14/16nm technology node 3-D FinFET devices at foundries, 3-D memory devices such as 128Gb NAND Flash memory devices with 32-layers and 3-D stacked chips for form factor with >40% package area saving. Intel was first to production with 3-D bulk-FinFET devices at the 22nm technology node in 2011 and reported their SOC version for Chinese low-end smartphone market. Intel’s 2nd generation bulk-FinFET devices at 14nm node was introduced in Aug 2014 with their SOC version to follow. In Sept 2012 iPhone 5 was first to incorporate Sony’s 8M pixel 3-D stacked backside CMOS image sensor for rear-facing camera. In April 2015 Samsung Galaxy S6 incorporated 14nm technology node 3-D FinFET devices in the Exynos 7 Octa application processor and first 3-D ePOP (embedded package on package) which stacks AP+DRAM (3Gb LPDDR3)+Flash(128/64/32Gb)+eMMC (embedded multi-media card)+controller saving 40% area and use Sony’s 16M pixel 3-D stacked back-side CMOS image sensor for rear-facing camera and 5M pixel RWB image sensor for front-facing camera. Apple will introduce the iPhone 6s/7 in Sept 2015 with A9 application processor using 3-D FinFET devices with Samsung/Foundry 14nm technology node and TSMC 16FF+. 10nm technology node is expected in 2016 with higher mobility SiGe or Ge channel material then 7nm node in 2018 and gate-all-around nano-wire by 5nm node in 2020. To understand 3-D FinFET doping and high mobility channel material this paper will first review the current doping and Fin/channel mobility enhancement techniques used for 22nm FinFET production by Intel for both high performance logic and SOC devices and the changes they made for their 2nd generation 14nm FinFET. 3-D 8o tapered FinFET S/D extension conformal doping was achieved with high tilt ion implantation at >45 degree. Highest retained dose and improved Fin sidewall line-edge-roughness (LER) on the atomic level can be realized with Hydrogen annealing surface passivation. High dopant activation is also achieved with advanced annealing SPE techniques of amorphous implanted junctions. Other 3-D dopant methods such as plasma implantation, knock-in dopant and deposition doping with diffusion including monolayer doping were not successful due to poor dopant activation and severe surface dopant loss. FinFET channel mobility enhancement at 22nm node used (511) plane taper Fin with 55% eSiGe S/D compressive strain for PMOS and amorphous implant SPE residual stacking fault defect S/D tensile stressor for NMOS. For 14nm node taller vertical Fins without the (511) taper and still 55% eSiGe S/D for PMOS and now eS/D for NMOS which is full of stacking fault defects. At the 10nm or 7nm node direct higher mobility Fin/channel material (SiGe, Ge or III-V) is expected to be introduced followed by exploratory research of gate-all-around nanowire for 5nm technology node. 25% SiGe to 100% Ge high mobility Fin-channel material on Si wafers will be realized by traditional gas/vapor phase epitaxial growth techniques by chemical vapor deposition (CVD) in blanket, selective growth including aspect ratio trapping, Ge condensation or an alternative liquid phase epitaxial (LPE) regrowth of an amorphous material layer by melt solidification. At 5nm node Si, SiGe or Ge nano-wire gate-all-around devices. Finally a discussion on dopant activation in high mobility Ge and SiGe material with low junction leakage.

Enhanced Ge n+/p Junction Performance Using Cryogenic Phosphorus Implantation

In this paper, we present a detailed study of temperature-based ion implantation of phosphorus dopants in Ge for varying dose and anneal conditions through fabricated n+/p junctions and n-type MOSFETs (nMOSFETs). In comparison with room temperature (RT) (25 °C) and hot (400 °C) implantation, cryogenic (−100 °C) implantation with a dose of 2.2e15 $\mathrm{cm}^{-2}$ followed by a (400 °C) rapid thermal annealing leads to 1) lower junction leakage with higher activation energy and 2) lower sheet resistance with higher dopant activation and shallower junction depth. Gate-last Ge nMOSFETs fabricated using cryogenic implanted n+/p source/drain junction (2.2e15 $\mathrm{cm}^{-2}$ ) exhibit lower off-current (upto $5\times )$ and higher ON-current compared with RT (25 °C) and hot (400 °C) implanted nMOSFETs. This paper demonstrates that cryogenic implantation (−100 °C) can enable high-performance Ge nMOSFETs by alleviating the problems of lower activation and high diffusion of phosphorus in Ge.

Influence of device architecture on junction leakage in low-temperature process FDSOI MOSFETs

In this paper, we demonstrate low junction leakage for Fully Depleted Silicon On Insulator (FDSOI) devices fabricated with a low thermal budget (⩽650°C), which commonly exhibit leakage problems due to the presence of defects in or close to depletion regions. We show through both experimental data and Kinetic Monte Carlo (KMC) simulations that the reduction of the film thickness and Raised Source Drain (RSD) allow the elimination of defects in critical regions in spite of the reduced thermal budget in the very early stage of the anneal. KMC simulations also show that defects are annealed-out in this critical region even for 500°C anneals. Low temperature process appears then as a suitable process for advanced devices.

Pre-Amorphous Implant and Millisecond Annealing for NiPt Sheet Resistance and Junction Leakage Reduction

With the aggressive scale down of MOSFET junction depth, nickel silicide (incorporated with platinum) is finally coming into picture with its low resistivity and silicon consumption. The sheet resistance and junction leakage are always a tradeoff during nickel silicide process development. This article introduces a novel nickel silicide process scheme to achieve low sheet resistance and low junction leakage at the same time. PAI(Pre-Amorphous Implant) is applying for sheet resistance reduction; the well controlled low process temperature during PAI and MSA (Milli-second Annealing) maintain the low junction leakage level.

Simulations of Bulk FinFETs with Body Gate Controlling Punch through Leakage

An optimized structure of bulk FinFETs with low punch through leakage is studied by 3D-TCAD simulation. We use an additional gate, called body gate, to control the punch through leakage to achieve low junction leakage. Different body gate bias can be used to control FinFETs punch through leakage without additional dopant in the channel, leading to less random dopant fluctuation. A new process flow to make the bulk FinFET structure with body gate is also proposed.

Selective Nickel Silicide Wet Etchback Chemistry for Low Temperature Anneal Process

The salicide (self-aligned silicide) technology involves selective wet etching step of non-reacted metal with respect to metal silicides. It was introduced in MOSFET fabrication due to the increase of the source, drain and gate resistances with the reduction of device dimensions. The introduction of a low resistive silicide layer on these areas has become mandatory to meet device specifications. NiSi has been widely considered for sub-65nm technology nodes due to its low resistivity, low silicon consumption and low formation temperature [1-2]. The two step annealing sequence is common in the industry for nickel silicide application to control the reverse linewidth effect. However, since Ni is the diffusing element in the NiSi reaction, a first high temperature rapid thermal anneal (RTA) will inadvertently result in Ni lateral diffusion under the spacer towards the gate causing electrical shorts. Indeed, a first low temperature anneal could seriously limit the nickel lateral diffusion and prevent this phenomenon. Minimizing thermal budget by means of reducing the temperature has also been proven to lower junction leakage current [3].

Investigation on reduction technique of anomalous leakage current generation in CMOS image sensor adopting n-type substrate

We, authors report a study on the junction leakage current of CMOS image sensor adopting p-epi/n-sub structure. High leakage current (more than 100 μA) through the junction between p-epi and n-sub (at reverse bias) were observed with non-uniformed or jagged test patterns (dislodged slivers) of the chip sidewalls such as the metal burrs causing defective trap induced field or fringing field, playing as a role of the additional electrical path in our devices. In order to minimize the junction leakage current, we controlled the penetration (or cutting) depth of the sawing blade to remove the remaining test patterns through the wafer sawing process and treated our devices with n-type guard ring fabrication along the chip boundary to isolate the area including the defective sidewalls of the sawn wafer, thereby decreasing the leakage current dramatically. Thus, we could obtain our devices with the excellent low junction leakage to be more reliable products for the low power consumption.

High-Performance $\hbox{GeO}_{2}/\hbox{Ge}$ nMOSFETs With Source/Drain Junctions Formed by Gas-Phase Doping

We reveal that the MOVPE-based gas-phase doping can yield lower arsenic diffusion constant and lower leakage current n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /p junctions in Ge compared with conventional ion-implantation doping. Thus, the gas-phase doping is quite effective for realizing high-performance Ge n-channel MOSFETs. By using gas-phase doping for source/drain junction formation, the (100) GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ge nMOSFETs have achieved high electron mobility of 1020 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s while maintaining low junction leakage current and high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> . Furthermore, the (110) GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ge nMOSFETs have also shown high electron mobility and high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio.

Formation of Nickel Silicide from Direct-Liquid-Injection Chemical-Vapor-Deposited Nickel Nitride Films

Smooth, continuous, and highly conformal nickel nitride films were deposited by direct liquid injection (DLI)–chemical vapor deposition (CVD) using a solution of bis(-di--butylacetamidinato)nickel(II) in tetrahydronaphthalene as the nickel (Ni) source and ammonia as the coreactant gas. The DLI-CVD films grown on HF-last (100) silicon and on highly doped polysilicon substrates served as the intermediate for subsequent conversion into nickel silicide (NiSi), which is a key material for source, drain, and gate contacts in microelectronic devices. Rapid thermal annealing in the forming gas of DLI-CVD films formed continuous NiSi films at temperatures above . The resistivity of the NiSi films was , close to the value for bulk crystals. The NiSi films have remarkably smooth and sharp interfaces with underlying Si substrates, thereby producing contacts for transistors with a higher drive current and a lower junction leakage. Resistivity and synchrotron X-ray diffraction in real-time during annealing of films showed the formation of a NiSi film at about , which is morphologically stable up to about . These NiSi films could find applications in future nanoscale complementary metal oxide semiconductor devices or three-dimensional metal-oxide-semiconductor devices such as Fin-type field effect transistors for the 22 nm technology node and beyond.

Germanium $\hbox{n}^{+}/\hbox{p}$ Diodes: A Dilemma Between Shallow Junction Formation and Reverse Leakage Current Control

This paper shows that germanium n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /p shallow junction formation often results in poor leakage current control. It is due to the counteraction between the fast diffusion of phosphorus and the high-temperature annealing requirement for dopant activation and defect annihilation. When the dopant concentration is above a threshold value, the concentration-dependent diffusion enhances phosphorus diffusion and results in a box profile, leading to an electrical concentration lower than its solid solubility limit. A refrained thermal budget may increase the active concentration, but it is not sufficient to repair the implantation-damaged lattice. Moreover, any plasma-involved fabrication processes after rapid thermal annealing may introduce additional field-assisted defects into the depletion region when the junction is near the surface. Thus, several tradeoffs must be considered between high P activation, low junction leakage, and a shallow junction in order to obtain functional negative-channel metal-insulator-semiconductor field-effect transistors.

Hybrid Integration of Ultrathin-Body Partially Insulated MOSFETs and a Bulk MOSFET for Better IC Performance: A Multiple-$V_{\rm TH}$ Technology Using Partial SOI Structure

The hybrid integration of ultrathin-body partially insulated MOSFETs (UTB PiFETs) and a bulk MOSFET was investigated. With a partial silicon-on-insulator (SOI) process using a SiGe sacrificial layer, UTB PiFETs with thin buried insulation layers were realized on the same bulk Si wafer with a bulk MOSFET. A partially insulating oxide (PiOX)-under-channel PiFET is suitable from the viewpoint of high-speed operation due to its SOI-like characteristics. On the other hand, a PUSD PiFET is useful from the viewpoint of low stand-by power operation due to its low junction leakage current. Through hybrid integration, not only multiple V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> 's can be obtained but also the technical difficulties of bulk MOSFETs can be alleviated. Thus, hybrid integration is a very useful process technique to implement integrated-circuit products with optimized power and performance management.

Enhancement mode GaAs metal-oxide-semiconductor field-effect-transistor integrated with thin AlN surface passivation layer and silicon/phosphorus coimplanted source/drain

By using thin AlN film as a passivation layer between the GaAs and HfO2, GaAs metal-oxide-semiconductor (MOS) devices exhibited well-behaved accumulation and inversion capacitance-voltage characteristics with low leakage current of 6×10−5A∕cm2 at Vg=1V and interface state density of ∼4.9×1010cm−2eV−1. In order to improve the N+ source/drain activation efficiency, the Si∕P coimplantation technique was adapted to fabricate GaAs n-type metal-oxide-semiconductor field-effect-transistor (MOSFET). High quality N+∕P GaAs junction was achieved with extremely low junction leakage current of 3×10−6A∕cm2 at reverse bias of 1V and high forward current to reverse current ratio of Iforward∕Ireverse∼107 at GaAs source/drain junction. GaAs n-MOSFETs integrated with HfO2 gate dielectric and TaN gate electrode were fabricated by using AlN passivation layer and Si∕P coimplantation techniques. The results show that our GaAs n-MOSFETs operate in enhancement mode with Ion∕Ioff ratio of approximately six orders and good transfer and output characteristics.

Effects of B or Al Interface Layers on Thermal Stability of Ni Silicide on Si

A new method is proposed to address the degradation of thermal stability in Ni silicide on heavily doped N-type Si substrates. Layered deposition of Al or B at the Ni/Si interface prior to silicidation was found to improve the thermal stability of Ni silicide, as evaluated by the sheet resistance vs. silicidation temperature properties. The improvement is attributed to suppression of the agglomeration of silicide layers. An Al layer was effective only when it was located at the Ni/Si interface prior to the silicidation process. The use of a B layer was preferable to that of Al when considering lower junction leakage.

Improved Electrical Characteristics of Ge-on-Si Field-Effect Transistors With Controlled Ge Epitaxial Layer Thickness on Si Substrates

The authors report on the novel MOSFETs that were fabricated on thin relaxed Ge epitaxial layers grown on Si substrates. With controlled epi-Ge thickness, selectively activated shallow source/drain (S/D) junctions are formed using low dopant activation energy of Ge. The Ge epitaxial layers determine the effective S/D junction depth by selectively activating S/D implantations only in the Ge layers, while suppressing activation in the Si substrates. Low junction leakage current and capacitance are also achieved by forming S/D junctions in Si substrates as well as in Ge layers with controlled epi-Ge thickness. With this technique applied to Ge-on-Si epitaxial layers, Ge pMOSFETs showed an improvement in short channel effects and junction characteristics.