Abstract

The salicide (self-aligned silicide) technology involves selective wet etching step of non-reacted metal with respect to metal silicides. It was introduced in MOSFET fabrication due to the increase of the source, drain and gate resistances with the reduction of device dimensions. The introduction of a low resistive silicide layer on these areas has become mandatory to meet device specifications. NiSi has been widely considered for sub-65nm technology nodes due to its low resistivity, low silicon consumption and low formation temperature [1-2]. The two step annealing sequence is common in the industry for nickel silicide application to control the reverse linewidth effect. However, since Ni is the diffusing element in the NiSi reaction, a first high temperature rapid thermal anneal (RTA) will inadvertently result in Ni lateral diffusion under the spacer towards the gate causing electrical shorts. Indeed, a first low temperature anneal could seriously limit the nickel lateral diffusion and prevent this phenomenon. Minimizing thermal budget by means of reducing the temperature has also been proven to lower junction leakage current [3].

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