Investigation on reduction technique of anomalous leakage current generation in CMOS image sensor adopting n-type substrate

Abstract

We, authors report a study on the junction leakage current of CMOS image sensor adopting p-epi/n-sub structure. High leakage current (more than 100 μA) through the junction between p-epi and n-sub (at reverse bias) were observed with non-uniformed or jagged test patterns (dislodged slivers) of the chip sidewalls such as the metal burrs causing defective trap induced field or fringing field, playing as a role of the additional electrical path in our devices. In order to minimize the junction leakage current, we controlled the penetration (or cutting) depth of the sawing blade to remove the remaining test patterns through the wafer sawing process and treated our devices with n-type guard ring fabrication along the chip boundary to isolate the area including the defective sidewalls of the sawn wafer, thereby decreasing the leakage current dramatically. Thus, we could obtain our devices with the excellent low junction leakage to be more reliable products for the low power consumption.