Low Interface Trap Density Research Articles

Low Interface Trap Density 4H-SiC MIS Structure With SiO₂ Grown by Sub- 1000 °C Intermittent Spray Hydrated Oxidation (ISHO) for UV Sensor Applications

Low Interface Trap Density 4H-SiC MIS Structure With SiO₂ Grown by Sub- 1000 °C Intermittent Spray Hydrated Oxidation (ISHO) for UV Sensor Applications

Enhanced Electrical Performance of InAs Nanowire Field-Effect Transistors Based on the Y2O3 Isolation Layer.

Nanowire (NW) field-effect transistors (FETs) have great potential in next-generation integrated circuits. InAs NWs are suitable for N-type transistors because of their excellent electrical properties. However, unlike the Si/SiO2 system, the loose and defective native oxide of InAs is unable to passivate the channel surface and serve as an efficient isolation layer (IL) in the gate stack. Here, we, for the first time, demonstrate that using a stable dielectric Y2O3 to replace the native oxide IL can effectively passivate the NW surface, isolate the channel surface from high-k HfO2, and improve the electrical properties of InAs NW FETs significantly. First, top-gate devices with Y2O3 IL outperform the devices with native oxide or chemically generated oxide of InAs as the IL, exhibiting a small subthreshold swing (SS) of 77 mV/dec, a large on-off ratio, a high field-effect mobility (μFE) of 1845 cm2/V·s, and an extremely low interface trap density (Dit) of 9.1 × 1011 eV-1 cm-2. Double-gate FETs with Y2O3 IL also show excellent gate control (drain-induced barrier lowering (DIBL) down to 35 mV/V) and a high μFE of 2711 cm2/V·s (the highest in the multigate structure). In addition, InAs NW FETs with Y2O3 IL show greater stability after long-term air exposure than those with native oxide IL, demonstrating retained on-off ratio, DIBL, transconductance, and even smaller SS (from 89 to 77 mV/dec). Finally, the results of low-temperature measurement suggest that Y2O3 IL can effectively improve interface qualities. Our results indicate that Y2O3/HfO2 InAs NW FETs have great potential in digital units of integrated circuits for future nodes. Our strategy for improving the interface between InAs NW and the dielectric layer is also valuable for other III-V NW devices.

Self‐Assembled Monolayer Dyes for Contact‐Passivated and Stable Perovskite Solar Cells

AbstractSurface modification of transparent conductive oxides (TCOs) with carbazole‐based self‐assembled monolayers (SAMs) is an effective method toward the formation of highly efficient hole‐selective contacts, enabling the fabrication of high‐performance perovskite solar cells (PSCs). However, the lack of long‐term structural and performance stability of the TCO/SAM/perovskite stack endangers the market entry of PSCs. Here, it is demonstrated that these challenges can be overcome by employing dyes as multi‐functional SAMs, simultaneously facilitating charge transport, passivating interfacial defects, and acting as a “molecular adhesive” layer, preserving structural integrity of the contact stack. Particularly, the surface modification of ITO with a dye (N719) monolayer is shown to create a hole‐selective contact for the fabrication of p–i–n PSCs with power conversion efficiencies reaching 24%. The N719 SAM‐based PSCs have also shown superior stability compared to state‐of‐the‐art PSCs incorporating carbazole SAMs and polyarylamine hole‐selective contacts by preserving ≈90% of their initial PCE under continuous light and thermal stress tests for 1000 h. The robustness of the ITO/N719/perovskite stack is attributed to its low interfacial trap density, UV resilience and strong adhesion capability. These findings place dye SAMs as a promising alternative for improving the performance of next‐generation photovoltaics.

Wafer-bonded In0.53Ga0.47As/GaN p–n diodes with near-unity ideality factor

III–V/III-nitride p–n junctions were realized via crystal heterogeneous integration, and the resulting diodes were characterized to analyze electrical behavior and junction quality. p-type In0.53Ga0.47As, which is a well-established base layer in InP heterojunction bipolar transistor (HBT) technology, was used in combination with a homoepitaxial n-type GaN. The latter offers low dislocation density, coupled with high critical electric field and saturation velocity, which are attractive for use in future HBT collector layers. Transmission electron microscopy confirms an abrupt interface in the fabricated heterogeneous diodes. Electrical characterization of the diodes reveals a near-unity ideality factor (n ∼ 1.07) up to 145 °C, a high rectification ratio of ∼108, and a low interface trap density of 3.7 × 1012 cm−2.

Atom-Scaled Hafnium Doping for Strengthening the Germanium Oxide Interfacial Layer of The Gate Stack of Germanium P-Type Metal-Oxide-Semiconductor Field Effect Transistor

We have developed a method that uses a half-cycle Hf precursor adsorption to subtly dope GeO2 IL of the Hf-based gate stack through in situ plasma-enhanced atomic layer deposition. This technique can effectively reduce GeO vaporization and improve the thermal stability of the GeO2 layer. Our results indicated that the accumulation capacitance (Cacc) undergoing higher temperatures showed no noticeable increase in the capacitance-voltage (CV) curves once Hf was delicately introduced into the GeO2 layer. According to the Ge 3d spectra of X-ray photoelectron spectroscopy, we found that the IL had a signal from extra Hf-O bonds; thus, we conclude GeO evaporation can be suppressed substantially by Hf incorporation. As a result, adding metal into GeOx IL to form HfGeOx achieved a remarkably low leakage current of 9 × 10−5 A cm−2 and the lowest interface trap density (Dit) of approximately 2 × 1011 eV−1 cm−2 at 500 °C of PMA. In addition, applying this gate stack structure to device fabrication significantly reduced the leakage current of the off-state and improved the effective peak hole mobility.

Achieving low-voltage operating high-mobility organic thin-film transistors by a multi-layered gate dielectric

Organic thin-film transistors (OTFTs) have attracted great attention for their inherent advantages and promising applications in emerging fields. Simultaneously realizing low-voltage operation and high-mobility in one OTFT is one of prerequisites for the commercialization, which is a huge challenge so far. An important route to address this challenge is to develop an ideal gate dielectric with a high capacitance and a low interfacial trap density at the dielectric/channel. In this Letter, we demonstrate the low-voltage operating high-mobility OTFTs by elaborately designing and processing a multi-layered gate dielectric. The gate dielectric consists of a high permittivity polymer film, a polymer buffing layer with a high surface energy, and an ultrathin long-chain alkane buffer layer. The effects of both the structures and the processes of gate dielectrics on the performances of OTFTs are investigated in detail. In addition, the relevant physical mechanisms are discussed. Finally, the optimal OTFTs exhibit high mobilities with the average and maximum values up to 5.62 and 6.74 cm2/V s, respectively, at low operating voltages below −5 V. Our findings reveal that designing and processing a reasonable multi-layered gate dielectric is a promising strategy to achieve both high-mobility and low-voltage operation in OTFTs, thereby fostering their development.

Optimizing interface properties of HfO2/Si0.73Ge0.27 gate stacks through sulfur passivation and post-deposition annealing

This paper presents a comprehensive exploration of low interface trap density (Dit) in HfO2/Si0.73Ge0.27 metal-oxide semiconductor (MOS) capacitors achieved through sulfur passivation and post-deposition annealing (PDA). Our investigation revealed that devices subjected to sulfur passivation and PDA exhibit noteworthy reductions in Dit and hysteresis. Specifically, a low Dit value of 1.2 × 1011 eV−1 cm−2 has been achieved at Ei–0.1 eV for the SiGe MOS device. The observed enhancement in interface properties can be attributed to two key factors: the reduction of the GeOx concentration in the interfacial layer (IL) by sulfur passivation on the SiGe surface and the IL densification with stoichiometric oxygen during PDA.

Effective passivation of p- and n-type In0.53Ga0.47As in achieving low leakage current, low interfacial traps, and low border traps

We have attained low leakage current, low interfacial traps, and low border traps by effectively passivating both p- and n-In0.53Ga0.47As (InGaAs) surfaces using the same gate dielectrics of ultra-high-vacuum deposited Al2O3/Y2O3. Gate leakage currents below 2 × 10−7 A/cm2 at gate fields of ±4 MV/cm were obtained after 800 °C rapid thermal annealing, demonstrating the intactness of the interface and heterostructure. Negligibly small frequency dispersions in the capacitance–voltage (C–V) characteristics of p- and n-type metal-oxide-semiconductor capacitors (MOSCAPs) were obtained from accumulation, flatband, to depletion as measured from 300 K to 77 K, indicative of low border and interfacial trap density; the C–V frequency dispersions in the accumulation region are 1.5%/dec (300 K) and 0.19%/dec (77 K) for p-InGaAs, and 2.2%/dec (300 K) and 0.97%/dec (77 K) for n-InGaAs. Very low interfacial trap densities (Dit's) of (1.7–3.2) × 1011 eV−1cm−2 and (6.7–8.5) × 1010 eV−1cm−2, as extracted from the conductance method, were achieved on p- and n-InGaAs MOSCAPs, respectively.

Coaxial boron nitride nanotubes as interfacial dielectric layers to lower interface trap density in carbon nanotube transistors

A semiconductor/dielectric interface is one of the dominant factors in device characteristics, and a variety of oxides with high dielectric constants and low interface trap densities have been used in carbon nanotube transistors. Given the crystal structure of nanotubes with no dangling bonds, there remains room to investigate unconventional dielectric materials. Here, we fabricate carbon nanotube transistors with boron nitride nanotubes as interfacial layers between channels and gate dielectrics, where a single semiconducting nanotube is used to focus on switching behaviors at the subthreshold regime. The subthreshold swing of 68 mV·dec−1 is obtained despite a 100-nm-thick SiO2 dielectric, corresponding to the effective interface trap density of 5.2 × 1011 cm−2·eV−1, one order of magnitude lower than those of carbon nanotube devices without boron nitride passivation. The interfacial layers also result in the mild suppression of threshold voltage variation and hysteresis. We achieve Ohmic contacts through the selective etching of boron nitride nanotubes with XeF2 gas, overcoming the trade-off imposed by wrapping the inner nanotubes. Negligible impacts of fluorinating carbon nanotubes on device performances are also confirmed as long as the etching is applied exclusively at source/drain regions. Our results represent an important step toward nanoelectronics that exploit the advantage of one-dimensional van der Waals heterostructures.

Large-Scale β-Ga2O3 Trench MOS-Type Schottky Barrier Diodes with 1.02 Ideality Factor and 0.72 V Turn-On Voltage

β-Ga2O3 Schottky barrier diodes (SBDs) suffer from the electric field crowding and barrier height lowering effect, resulting in a low breakdown voltage (BV) and high reverse leakage current. Here, we developed β-Ga2O3 trench MOS-type Schottky barrier diodes (TMSBDs) on β-Ga2O3 single-crystal substrates with halide vapor phase epitaxial layers based on ultraviolet lithography and dry etching. The 1/C2−V plots are deflected at 2.24 V, which is caused by the complete depletion in the mesa region of the TMSBDs. A close-to-unity ideality factor of 1.02 and a low turn-on voltage of 0.72 V are obtained. This is due to the low interface trap density in the metal/semiconductor interface of TMSBDs, as confirmed by the current–voltage (I–V) hysteresis measurements. The specific on-resistance calculated with the actual Schottky contact area increases as the area ratio (AR) increases because of the current spreading phenomenon. Furthermore, the reverse leakage current of the TMSBDs is smaller and the BV is increased by 120 V compared with the regular SBD. This work paves the way for further improving the overall performance of β-Ga2O3 TMSBDs.

Role of interface and bulk traps on the capacitance–voltage characteristics of WS2/Al2O3/Si capacitors

This paper reports the capacitance–voltage (CV) characteristics of 2D material based vertical semiconductor-oxide semiconductor (SOS) capacitors (CAPs) at different ac frequencies. The SOS structure is made of mechanically exfoliated WS2 flakes, deposited on a p-type silicon substrate covered by Al2O3 dielectric layer. The device exhibits n-type behavior as WS2 goes into accumulation at positive biases on the p-Si, with a non-intentional doping concentration of around 1017cm-3. By double sweeping the DC bias, a hysteresis cycle occurs in the CV response. On the other hand, a low frequency dispersion is observed in the depletion mode implying a low WS2/Al2O3 interface trap density. Our quantitative analysis confirms a low interface trap density of Dit∼1011cm-2eV-1. We also report our observation on a distortion in the CV characteristics, observed as the depletion width expands into the WS2 at negative voltage bias. This feature does not depend on the ac signal frequency. Based on our CV analysis, we have proposed a hypothesis with a schematic band-energy model where the CV distortion is attributed to localized bulk traps in the WS2 located within the first few nm from the WS2/Al2O3 interface.

Carrier Trap Density Reduction at SiO2/4H-Silicon Carbide Interface with Annealing Processes in Phosphoryl Chloride and Nitride Oxide Atmospheres.

The electrical and physical properties of the SiC/SiO2 interfaces are critical for the reliability and performance of SiC-based MOSFETs. Optimizing the oxidation and post-oxidation processes is the most promising method of improving oxide quality, channel mobility, and thus the series resistance of the MOSFET. In this work, we analyze the effects of the POCl3 annealing and NO annealing processes on the electrical properties of metal-oxide-semiconductor (MOS) devices formed on 4H-SiC (0001). It is shown that combined annealing processes can result in both low interface trap density (Dit), which is crucial for oxide application in SiC power electronics, and high dielectric breakdown voltage comparable with those obtained via thermal oxidation in pure O2. Comparative results of non-annealed, NO-annealed, and POCl3-annealed oxide-semiconductor structures are shown. POCl3 annealing reduces the interface state density more effectively than the well-established NO annealing processes. The result of 2 × 1011 cm-2 for the interface trap density was attained for a sequence of the two-step annealing process in POCl3 and next in NO atmospheres. The obtained values Dit are comparable to the best results for the SiO2/4H-SiC structures recognized in the literature, while the dielectric critical field was measured at a level ≥9 MVcm-1 with low leakage currents at high fields. Dielectrics, which were developed in this study, have been used to fabricate the 4H-SiC MOSFET transistors successfully.

Analysis of trap distribution and NBTI degradation in Al2O3/SiO2 dielectric stack

In this work, p-substrate MOS capacitors with plasma-enhanced atomic-layer-deposited Al2O3/ thermally-grown SiO2 dielectric stack (with a target equivalent oxide thickness of 4.2 nm) are investigated by means of the conductance method in a temperature range from 25 °C to 150 °C. The trap state density and energy level distribution in the silicon bandgap are extracted over the bandgap. Furthermore, negative bias temperature instability is analyzed by two-point capacitance–voltage characterization to evaluate the electrical stability and dielectric reliability of the Al2O3/SiO2 stack. The contributions from interface and oxide trap generations are detailed. Our results indicate that plasma-enhanced atomic layer deposited Al2O3 on thermal SiO2 stack features low interface trap density, and comparable dielectric reliability to conventional SiO2, SiOxNy, and high-k dielectric stacks.

Alteration in growth temperatures of metal-organic decomposed GaxCe1-xOyNz passivation layer in nitrogen/oxygen/nitrogen ambient

A quantitative analysis of the morphology, topography, and electrical characterization of the metal-organic decomposed quaternary GaxCe1-xOyNz passivation layer grown on Si substrate in nitrogen/oxygen/nitrogen ambient at temperatures of 600, 700, 800, and 900 °C was carried out. Incorporation of nitrogen into the passivation layer was more prominent at lower temperatures by either attaching to oxygen vacancies sites or staying as dangling bonds in the passivation layer. The increase of annealing temperature to 800 and 900 °C enhanced the adsorption of oxygen to occupy the oxygen vacancies and hence, limiting the incorporation of nitrogen. As a consequence, formation of SiO2 took place at the interface between GaxCe1-xOyNz and Si substrate, degrading the k value of the passivation layer. The largest k value was perceived by the passivation layer annealed at 700 °C, accompanied with the acquisition of the highest positive effective oxide charges and considerably low interface trap densities and low trap density as well as large band gap, which led to an improvement in the current density-electric field (J-E) performance.

Photovoltaic Performance of Si and SiGe Surfaces Sonochemically Activated in Dichloromethane

Aims: To activate Si and SiGe surfaces by employing the sonochemical treatment at different operating frequencies in dichloromethane to improve the surface photovoltage signal. Background: To produce integrated electronic devices, one needs to achieve low surface and interface trap densities. In this respect, placing a passivating thin layer on Si and Ge surfaces, which saturates the electronic levels of traps and therefore affects the carrier recombination velocities at the surface, is of great interest. Objective: To demonstrate that the effectiveness of the treatment of Si and SiGe surfaces depends on the ultrasonic frequency used. Methods: Photovoltaic transients, electron microscopy, EDX spectroscopy. Result: The surface photovoltage (SPV) decay curves can be divided into rapid (τ_1) and slow (τ_2) components. The sonication effect on the SPV is different for the treatment done at about 25 and 400 kHz. The SPV signal in Si gradually increases with increasing lower-frequency sonication time, whereas the SPV enhancement on SiGe is somewhat smaller. Increasing the sonication time increases the amplitude of the τ_2 component in Si. In SiGe, the lower-frequency sonication quenches the τ_2 component yielding a nearly single-exponential decay form. This trend is even more pronounced at the higher-frequency sonication. Conclusion: The sonochemical treatments greatly intensify the formation of CxHy–Si and CxHy–Ge bonds on Si and Si1-xGex surfaces, resulting in increased SPV signals and prolonged SPV decay times. These results demonstrate that sonochemical treatment is a more effective technique to obtain stable highly passivated Si and Si1-xGex surfaces in comparison with wet chemical treatments in hydrocarbon solutions.

Metal-organic decomposed cerium oxide thin film in mixed ambient at different temperatures for MOS capacitor

Post-deposition annealing of CeO2 thin films in nitrogen/oxygen/nitrogen ambient from 400 until 1000 °C successfully transformed the films from oxygen poor to oxygen-rich state, in which an excess of oxygen was detected at higher temperatures as the oxygen interstitials. The adsorbed nitrogen attaching to oxygen vacancies in the CeO2 thin films would inhibit further oxidation of the films, and thus controlling the film thickness in addition to expanding the lattice. The increase of temperature has enhanced adsorption and diffusion of nitrogen and oxygen, decreasing the attachment of nitrogen to the oxygen vacancies. The dissociated nitrogen would reside as dangling bonds that caused a difficulty in controlling the oxidation and hence interfacial layer growth was expected. An exaggerated film growth dominated by interfacial layer happened at the highest temperature, surpassing the CeO2 layer thickness. The lowest interface trap density was attained but a degradation in the current-voltage characteristic happened due to the presence of excess oxygen and nitrogen as the scattering center for the incoming electrons during forward bias operation. A better performance was achieved by the film annealed at 800 °C via the demonstration of the lowest leakage current level, surpassing other films. Detailed explanation was discussed in this work.

A perspective study on Au-nanoparticle adorned TiO2-nanowire for non-volatile memory devices

In this article, we synthesized Au-nanoparticle (NP) adorned TiO 2 -nanowire (NW) and TiO 2 -NW using glancing angle deposition technique (GLAD) for capacitive memory based application. To analyze memory performance of the device, capacitance (C) versus voltage (V) and conductance (G) versus voltage (V) characteristics were performed at various frequency up to 2 MHz. Consequently, we analyzed C-V hysteresis loop at different sweep voltages from ±2 V to ±10 V. The device Au-NP adorned TiO 2 -NW shows a large memory window (MW) of 12.65 volt at ±10 V and low interface trap density (D it ) of ⁓2.63×10 11 eV -1 cm -2 at 1 MHz operating frequency. The endurance and retention were calculated for both the samples. A higher endurance and stable retention were observed for Au-NP adorned TiO 2 -NW as compared to TiO 2 -NW. The results presented in this article established a strong presence of non-volatile memory based characteristics.

Methodology for Enhanced Surge Robustness of 1.2-kV SiC MOSFET Body Diode

In this work, the influences of P-well design and turn-off gate-to-source bias on the surge robustness of SiC MOSFET’s body diode are studied. Devices with high and low P-well doping concentration designs are stressed with surge current pulses when the gate-to-source is biased with 0 or −5 V. The gate-to-source bias is found to have effects on the surge capability of the low P-well doping-designed device. In the case of 0-V bias, the channel is prone to turning on and acquires a higher surge capability than the devices under the −5 V. On the other hand, the surge capability of high P-well doping-designed device is found less influenced by the gate-to-source bias. Furthermore, threshold voltage instability after repetitive surge pulses is also investigated. The device with low P-well doping shows better threshold stability due to its lower interface trap density. Based on the results above, a design methodology is proposed from the view of device mechanism and operation condition. Relatively low P-well doping design and negative gate bias are recommended for SiC MOSFET, as they can improve the single-pulse surge robustness of body diode and minimize the threshold voltage instability in repetitive surge pulse events.

Growth of Quaternary GaxCe1-xOyNz passivation layer for silicon based metal-oxide-semiconductor capacitor

Quaternary GaxCe1-xOyNz passivation layer was successfully grown on silicon substrate after annealing in nitrogen-oxygen-nitrogen (NON) ambient at 800 °C. The employment of NON ambient has managed to impede the diffusion of oxygen ions to the interface, and thus suppressing the formation of interfacial layer (IL), which eventually led to the acquisition of k value of 8.7. Furthermore, an improvement in interface quality was perceived as a lower interface trap density (Dit; 2.9 x 1012 eV−1 cm−2) was attained by this GaxCe1-xOyNz layer when compared with previously reported CeO2 layer (4.0 x 1012 eV−1 cm−2). Detailed investigation of the passivation layer was discussed in this manuscript.

Low temperature silicon nitride grown by very high frequency (VHF, 162MHz) plasma enhanced atomic layer deposition with floating multi-tile electrode

Important issues for silicon nitride (SiNx) plasma enhanced atomic layer deposition (PEALD) are lowering the process temperature and minimization of plasma damage. In this study, the characteristics of PEALD SiNx films deposited at a low processing temperature of 100 °C with di-isopropylamino silane (DIPAS) and N2 plasma excited by using a very high frequency (VHF, 162 MHz) floating multi-tile electrode capacitively coupled plasma (CCP) source and a conventional VHF CCP source are reported in addition to the characteristics of both plasma sources. The PEALD SiNx film deposited with the floating multi-tile electrode exhibited higher growth rate (∼ 0.6 Å/cycle), higher N/Si ratio film (N/Si ∼ 0.98, even though it is lower than the stoichiometric ∼1.33 of N/Si for Si3N4) with no trace of carbon, lower surface roughness, and higher conformality in a trench compared to those deposited by the conventional CCP. In addition, improved electrical properties of the SiNx films such as lower leakage current, lower interface trap density, and higher breakdown voltage of PEALD SiNx film were obtained with the floating multi-tile electrode. These enhanced properties of SiNx films deposited by the floating multi-tile electrode are believed to be related to the higher plasma density, higher radical density, and lower ion energy bombarding the substrate observed for the multi-tile electrode through the enhanced power efficiency of the differentially-coupled multi-tile plasma source.