Methodology for Enhanced Surge Robustness of 1.2-kV SiC MOSFET Body Diode

Abstract

In this work, the influences of P-well design and turn-off gate-to-source bias on the surge robustness of SiC MOSFET’s body diode are studied. Devices with high and low P-well doping concentration designs are stressed with surge current pulses when the gate-to-source is biased with 0 or −5 V. The gate-to-source bias is found to have effects on the surge capability of the low P-well doping-designed device. In the case of 0-V bias, the channel is prone to turning on and acquires a higher surge capability than the devices under the −5 V. On the other hand, the surge capability of high P-well doping-designed device is found less influenced by the gate-to-source bias. Furthermore, threshold voltage instability after repetitive surge pulses is also investigated. The device with low P-well doping shows better threshold stability due to its lower interface trap density. Based on the results above, a design methodology is proposed from the view of device mechanism and operation condition. Relatively low P-well doping design and negative gate bias are recommended for SiC MOSFET, as they can improve the single-pulse surge robustness of body diode and minimize the threshold voltage instability in repetitive surge pulse events.