Low Interface Trap Density Research Articles

GaN MOS Structures with Low Interface Trap Density

GaN based electronic devices have gained great success in the arena of high-frequency and high-power applications. A high-quality GaN MOS structure has the potential to enable new device designs and higher device performance, thereby bringing the success of GaN electronics to a new level. This paper discusses results of the work on GaN MOS structures show that with adequate surface preparation samples featuring interface trap density down to the ~ 1010 eV-1cm-2 range can be formed.

Effects of Al Composition and High-Temperature Atomic Layer-Deposited Al2O3 Layer on the Leakage Current Characteristics of AlGaN/GaN Schottky Barrier Diodes

AlGaN/GaN Schottky barrier diodes (SBDs) with high Al composition and high temperature atomic layer deposition (ALD) Al2O3 layers were investigated. Current–voltage (I–V), X-ray photoelectron spectroscopy (XPS), atomic force microscope (AFM), and capacitance–voltage (C–V) measurements were conducted in order to find the leakage current mechanism and reduce the reverse leakage current. The fabricated AlGaN/GaN SBDs with high Al composition exhibited two orders’ higher leakage current compared to the device with low Al composition (20%) due to large bulk and surface leakage components. The leakage current measured at −60 V for the fabricated SBD with Al2O3 deposited at temperature of 550 °C was decreased to 1.5 μA, compared to the corresponding value of 3.2 mA for SBD with nonpassivation layer. The high quality ALD Al2O3 deposited at high temperature with low interface trap density reduces the donorlike surface states, which effectively decreases surface leakage current of the AlGaN/GaN SBD.

An Interface-Induced Dielectric Properties Degradation in Heterogeneous Stacked Device With P(VDF-TrFE)-Based Ferroelectric Polymers

Heterogeneous stacked electronics are one of the major topics in flexible electronics applications, which require high performances. At the same time, P(VDF-TrFE)-based polymers with unique characteristics, e.g., ferroelectric and flexible properties, also bring attention to heterogeneous stacked device applications. Since the interfacial characteristic has strong effects with performance and reliability, therefore, it becomes one of the key issues in P(VDF-TrFE)-based heterogeneous stacked devices. In this article, a mechanism of an interface trap charge-induced low-k interfacial layer was proposed and examined by experimental methods. To analyze the low-k interfacial layer effects, both general-doping (few 1015 cm−3) p-type and n-type silicon substrate were used. These experimental results showed that different types of silicon substrates have distinct interface properties. Then, different interface trap density ( $1.75\times 10^{12}$ – $4.1\times 10^{11}$ eV−1 cm−2) silicon substrates were fabricated to further analyze the low-k interfacial layer. These showed the substrate with the lowest interface trap density has less low-k interfacial effect than other substrates do. Based on these experimental verifications, the mechanism of interface trap charge-induced low-k interface characteristic was proposed. As a consequence, this interface trap–charge-induced behavior is a necessary consideration for applications of heterogeneous stacked devices.

Formation of Intermediate SiO2 nano-Layer As Effective Passivation at Si/TiO2 Interface By Zone Heating Recrystallization Toward Perovskite/Silicon Tandem Solar Cell

A monolithic perovskite/c-Si tandem solar cell has attracted a lot of attention in the field of photovoltaic for its high theoretical energy conversion efficiency and cost-effectiveness. For this technology to reach its potential, optimization and compromised for both perovskite top cell and silicon bottom cell has to be investigated.In a single-junction perovskite solar cell, the hybrid organic-inorganic perovskite light-absorbing layer is sandwiched with electron and hole transporting layers (ETL and HTL). For optimal carrier extraction, the bandgap of the transporting layers has to match the perovskite material such that electron can be selectively transported to the ETL while only hole moves through HTL. In the majority of perovskite solar cells, titanium dioxide (TiO2) is used as ETL, for its high bandgap alignment, ease of fabrication, and low cost. For this reason, a tandem solar cell with c-Si/ETL(TiO2)/Perovskite/HTL structure has the potential to be highly efficient and low in cost [1].In a single-junction c-Si solar cell, surface passivation of silicon using large bandgap materials such as Al2O3, SiO2 or SiNx is widely known to reduce the velocity of carrier recombination and thus increase the carrier lifetime at silicon surface. This approach, however, is not applicable in tandem solar cells with c-Si/ETL/Perovskite/HTL structure, as the utilization of large bandgap materials in between c-Si and ETL causes bandgap misalignment and prevents interlayer exchange of carriers between perovskite and silicon cells. For this reason, a new approach that accommodates both interlayer exchange of carriers and passivate silicon surface effectively is required.In most of Si-Oxides (Al2O3, TiO2, ZnO, etc.) interface, the existence of SiOx layer is unavoidable and widely known due to high reactivity of silicon surface under oxidizing atmosphere [2]. Furthermore, while the improvement of perovskite solar cell efficiency by controlling spray pyrolysis of TiO2 and the thermal annealing procedure has been reported [3], prolonged exposure to heat during TiO2 fabrication might negatively affect the performance of silicon bottom cell, and thus requires further studies. Due to the high surface passivation effect of thermally grown SiO2 layer, we hypothesized that a proper crystallization of SiOx layer might be able to increase the lifetime of carrier at Si/TiO2 interface and mitigate the surface passivation problem in tandem solar cells with c-Si/ETL/Perovskite/HTL structure.Zone Heating Recrystallization (ZHR) is a process developed by our research group in which the surface of samples was selectively heated by the scanning of highly focus line lamp heater with elliptical mirror. Previously, we reported the utilization of ZHR to obtain smooth seed layers for thin-film silicon solar cell applications [4, 5] among other functionalities. The use of high-intensity lamp heater in ZHR process combines with high transparency of TiO2 layer makes ZHR a suitable process to selectively treat the Si/TiO2 interface and test our hypothesis on SiOx crystallization.With the introduction of ZHR, the minority carrier lifetime of Si/TiO2 interface was increased from less than 5 µs to more than 250 µs. Different scanning rates of lamp heater in ZHR process lead to different carrier lifetime, with higher scanning rates lead to higher carrier lifetime. To explain this phenomenon, cross-sectional TEM images of Si/TiO2 treated with different scanning rate was taken and analyzed. Here, we found that samples treated with higher scanning rates of ZHR have thinner SiOx layer and higher carrier lifetime. The relationship between SiOx thickness and carrier lifetime might be explained with the interface trap density of SiOx layer in which thinner layer shows lower interface trap density. This leads to lower carrier recombination velocity and therefore higher carrier lifetime at Si/TiO2 interface.References Mailoa J. P. et al., A 2-terminal perovskite/silicon multijunction solar cell enabled by a silicon tunnel junction. Appl. Phys. Lett. 106, 121105 (2015).Black L. E. et al., Explorative studies of novel silicon surface passivation materials: Considerations and lessons learned. Solar Energy Materials and Solar Cells 188, 182- 189 (2018).Nukunudompanich M., Ihara M. et al., Dominant effect of the grain size of the MAPbI3 perovskite controlled by the surface roughness of TiO2 on the performance of perovskite solar cell. CrysEngComm 22, 2718-2727 (2020).Ihara M. et al., Fabrication of silicon thin films with defects below detection limit of electron spin resonance for solar cells by high-speed zone-melting crystallization of amorphous silicon. Appl. Phys. Lett. 79, 3809 (2001).Lukianov A., Ihara M. et al., Formation of the seed layers for layer-transfer process silicon solar cells by zone-heating recrystallization of porous silicon structures. Appl. Phys. Lett. 108, 213904 (2016). Figure 1

Novel Band-Edge Work Function Performance Modulation via NPT with PMOS1st/NMOS1st Laminated Stack for PMOS Low Power Target

In this paper, the band-edge work function performance is systematically investigated and modulated via novel nitrogen plasma treatment (NPT) with the advanced PMOS1st (TiN/TiN/TiAlC) and NMOS1st (TiN/TiN) laminated stacks for the fabricated PMOS capacitors. The basic multi-VT performance is strongly modulated by controlling NPT process. 1) Flatband voltage (VFB) shifts towards band edge are obtained as +120 mV (undiluted), +430 mV (diluted) for PMOS1st and +80 mV (undiluted), +210 mV (diluted) for NMOS1st. 2) By manipulating the NPT process from undiluted and diluted case, it can provide significant high band-edge effective work function ranging from 4.89 eV (undiluted) to 5.21 eV (diluted) for PMOS1st and 5.22 eV (undiluted) to 5.35 eV (diluted) for NMOS1st laminated stack, respectively. 3) NPT diluted with hydrogen is observed to maintain ultralow bulk trap density (1.11 × 1011 cm−2 for PMOS1st and nearly zero for NMOS1st) and interface trap density (3.34 × 1011 eV−1 cm−2 for PMOS1st and 6.45 × 1011 eV−1 cm−2 for NMOS1st). The significant band-edge work function modulation and very low bulk and interface trap density demonstrate the novel NPT with PMOS1st/NMOS1st laminated stack is very promising to achieve the target of PMOS low-power application in the further technology node.

Surface termination effects on the electrical characteristics of La2O3/Al2O3 nanolaminates deposited by atomic layer deposition* *Project supported by the National Natural Science Foundation of China (Grant Nos. 61604016 and 51802025), China Postdoctoral Science Foundation (Grant No. 2017M613028), the Fundamental Research Funds for the Central Universities, China (Grant Nos. 300102319209 and 300102310501) and the Innovation, and Entrepreneurship Training Program for Undergraduates

Effects of initial surface termination on electrical characteristics of La2O3/Al2O3 nanolaminates deposited by atomic layer deposition are studied by conductive atomic force microscopy working in contact mode and standard electrical characterization methods. It is found that, compared with La2O3/Al2O3 nanolaminates with LaO x as termination, lower interface trap density, less current leakage spots, and higher breakdown voltage are obtained in the La2O3/Al2O3 nanolaminates with AlO x as termination after annealing. A clear promotion of interface silicate layer is observed for La2O3/Al2O3 nanolaminates with AlO x as termination compared with LaO x as termination under the same annealing condition. In addition, the current conduction mechanism in La2O3/Al2O3 nanolaminates is considered as the Poole–Frenkel conduction. All results indicate that the AlO x is a more appropriate termination to deposit La2O3/Al2O3 nanolaminates on Si substrate, which is useful for the high-κ process development.

Sol-gel-derived transparent metal oxide flexible field effect transistors.

ZnO and ZnO:Al thin films have been successfully synthesized by simple solution processable method at low temperature. Highly crystalline (002) preferentially oriented, uniform, and smooth ZnO:Al thin films are produced. The electrical, J-V and C-V, measurements revealed higher current flow and more carrier concentration, respectively, for ZnO:Al samples compared with pristine ZnO. ZnO- and ZnO:Al-based field effect transistors (FETs) were fabricated using SiO2 and TiO2 gate dielectric layers onto flexible plastic, ITO and rigid, p-Si substrates. The ZnO:Al-based FETs measured better transistor performance with both SiO2 and TiO2 gate dielectrics as compared with ZnO-based TFTs. The saturated field effect mobilities 5.78 and 4.96 cm2/Vs were measured for ZnO:Al-based TFTs with SiO2 and TiO2 dielectrics, which reasonably higher than 0.51 and 0.43 cm2/Vs, respectively, measured for pristine ZnO TFTs. The effect of smooth surface and reduced grain boundaries of ZnO:Al layer contributed to measure the low-interface trap density and trap density at grain boundaries. The reported procedure can be applicable to produce large area transparent electronics onto flexible plastic substrates.

Revealing Energy Loss and Nonradiative Recombination Pathway in Mixed-Ion Perovskite Solar Cells.

Multiple-cation lead mixed-halide perovskites (MLMPs) with tunable band gaps have been demonstrated as ideal candidates to achieve perovskite solar cells with high efficiencies. It is well-known that a large open-circuit voltage (VOC) loss caused by nonradiative recombination still limits the approach to the Shockley-Queisser limit. However, there are few comprehensive contributions regarding the origin and pathway of nonradiative recombination in n-i-p structured MLMPs. Here, we compare the performance of MLMPs containing different halides and analyze the energy loss and interface trap-assisted nonradiative recombination characterizations. It is found that Br-containing devices with a lower interface trap density of 3.2 × 1013 cm-2 obtain a high VOC of 1.12 V, a small energy loss of 0.02 eV, radiative recombination current density of 8.05 × 10-21 A m-2, and total recombination current density of 22.16 mA cm-2. This work provides an opportunity to understand the device physics and reveals the nature of nonradiative recombination based on experiment and simulation.

Comparison of electrical and interfacial characteristics between atomic-layer-deposited AlN and AlGaN on a GaN substrate

The electrical and interfacial characteristics of AlN/GaN and AlGaN/GaN heterostructures prepared by thermal atomic layer deposition (ALD) were investigated in this work. According to the parallel conductance method, the AlGaN/GaN sample showed two border traps with energies of ~ 0.38 and ~ 0.46 eV, which were not observed for the AlN/GaN sample. The AlN/GaN sample also showed a lower interface trap density and a lower reverse leakage current. X-ray photoelectron spectroscopy analysis indicated that during the initial ALD deposition process, most of the Al and N atoms tended to combine with oxygen atoms as opposed to Ga atoms. As a result, AlGaN layer formation was delayed, resulting in the creation of a defective interfacial layer at the AlGaN/GaN interface. Thus, our results indicate that the initial ALD process should focus on removing the defective interfacial layer during AlGaN deposition for device optimization.

Epitaxial growth of a silicon capping layer to mitigate roughness after the selective chemical etching of Si1-xGex

The gate-all-around structure is a promising candidate for future generations of advanced metal-oxide semiconductor field-effect transistor technologies, as it provides higher drive current and low-power operation. The commonly-suggested nanowire structure uses a selective etching technique in the silicon/silicon-germanium multilayer to reveal the channel area. The revealed Si surface is rough, however, due to the missing atoms and remnants of Si1-xGex. This leads to increased interfacial state density, which degrades device performance, such as subthreshold voltage swing. Regarding the usage of high-k metal gates on the channel area, the issue of this rough surface, and the subsequent increase of the dangling bonds after etching, should be properly addressed.In this study, we report the enhanced roughness and density of interface state by applying a Si capping layer. The epitaxial Si0.87Ge0.13 layer, with a thickness of 30 nm on the Si substrate, was removed by an etchant consisting of nitric acid, hydrofluoric acid, and acetic acid, after which a 1-nm thick Si capping layer was epitaxially grown onto the surface. Atomic Force Microscopy was used to measure the roughness, and X-ray Photoelectron Spectroscopy was conducted to characterize the atomic bonds on the surface. A 10-nm thick SiO2 film was deposited using the Atomic Layer Deposition process to characterize the capacitance-voltage curve and interface trap density. The Si-capped sample exhibited half of the surface roughness of the un-capped sample, and exhibited a 30% lower interface trap density, by mitigating the impact of wet etching.

ALD grown polycrystalline HfO2 dielectric layer on (−2 0 1) β-Ga2O3 for MOS capacitors

Polycrystalline HfO2 dielectrics grown on (−2 0 1) beta-gallium oxide (β-Ga2O3) using high temperature ALD process is investigated. A low capacitance–voltage (C-V) hysteresis of <60 mV is obtained, and the high quality interface is verified via the temperature-dependent C-V characterizations, showing low interface trap density (Dit < 1.3 × 1012 cm−2eV−1) distributions over the extended energy range. The proposed polycrystalline HfO2/(−2 0 1) β-Ga2O3 MOS structure can be an attractive candidate for β-Ga2O3 based MOSFET devices.

Rare Metal‐Free High‐Performance Zinc–Tin Oxide Thin Film Transistors Using Efficient Energy Conversion of Microwave Annealing

Herein, a rare metal‐free oxide‐based semiconductor channel layer is constructed with excellent electrical properties and stabilities by fabricating zinc–tin oxide (ZTO) thin film transistors (TFTs) using tin (Sn) as the dopant element in ZnO. Furthermore, to improve the performance and stability of ZTO TFTs, microwave annealing (MWA) powered by energy conversion from electromagnetic energy to heat energy rather than heat transfer is conducted as the post‐deposition annealing (PDA) process of the ZTO channel layer. As a result, the electrical performance of ZTO TFTs is improved by MWA despite the much shorter PDA time because of the efficient energy transfer compared with that of furnace‐used thermal annealing (FTA) in conventional furnaces. The ZTO TFTs subjected to MWA exhibit a high on/off current ratio of 1.7 × 107, a high field‐effect mobility of 20.6 cm2 V−1 s−1, a small hysteresis voltage of 0.9 V, and a low interface trap density of 1.8 × 1012 cm−2 eV−1. In addition, the instabilities due to the positive and negative gate bias stresses at various operating temperatures are evaluated, and the results show that the instability of the ZTO TFT is significantly reduced by MWA.

Temperature-dependent study of slow traps generation mechanism in HfO2/GeON/Ge(1 1 0) metal oxide semiconductor devices

The lower mobility for p-type Ge based is always an issue due to slow traps generation at the interface of the metal oxide semiconductor (MOS) device which designates the defects in films generated during the deposition process. One of the effective ways to reduce this slow traps generation is to perform post deposition annealing (PDA) at a certain temperature. However, the selection of proper annealing temperature is the key to reduce defects without damaging the film quality. The effect of different PDA temperatures on the slow traps generation mechanism in the GeON passivated Ge MOS device was examined in this work. The XPS spectra show the stable formation of GeON over Ge, while HRTEM does not show any effect of PDA at the interface of GeON/Ge. The slow trap density (ΔNst) in HfO2/GeON/Ge interface annealed at different temperatures was evaluated from the hysteresis curve of C-V sweep as the function of the effective oxide field. The lowest ΔNst (4.01 × 1012 cm−2) was observed for the PDA temperature for 400 ℃. While, ΔNst increased slightly after PDA at 450 ℃. The work suggests that PDA at lower temperatures is essential to realize the high quality interface with lower interface trap density, enhanced mobility and lower CET in Ge based MOS devices. Further, it also helps to reduce the slow traps generations at the interface.

Influence of Ultra-Thin Ge₃N₄ Passivation Layer on Structural, Interfacial, and Electrical Properties of HfO₂/Ge Metal-Oxide-Semiconductor Devices.

We report the effects of the nitride passivation layer on the structural, electrical, and interfacial properties of Ge metal-oxide-semiconductor (MOS) devices with a hafnium oxide (HfO₂) gate dielectric layer deposited on p-type 〈100〉 Ge substrates. X-ray photoelectron spectroscopy analysis confirmed the chemical states and formation of HfO₂/Ge₃N₄ on Ge. The interfacial quality and thickness of the layers grown on Ge were confirmed by high-resolution transmission electron microscopy. In addition, the effects of post-deposition annealing (PDA) on the HfO₂/Ge₃N₄/Ge and HfO₂/Ge samples at 400 °C in an (FG+O₂) ambient atmosphere for 30 min were studied. After PDA, the HfO₂/Ge₃N₄/Ge MOS device showed a higher dielectric constant (k) of ~21.48 and accumulation capacitance of 1.2 nF, smaller equivalent oxide thickness (EOT) of 1.2 nm, and lower interface trap density (Dit) of 4.9×1011 cm-2 eV-1 and oxide charges (Qeff) of 7.8×1012 cm-2 than the non-annealed sample. The I-V analysis showed that the gate leakage current density of the HfO₂/Ge₃N₄/Ge sample (0.3-1 nA cm-2 at Vg = 1 V) was half of that of the HfO₂/Ge sample. Moreover, the barrier heights of the samples were extracted from the Fowler-Nordheim plots. These results indicated that nitride passivation is crucial to improving the structural, interfacial, and electrical properties of Ge-based MOS devices.

Rear surface passivation of ultra-thin CIGS solar cells using atomic layer deposited HfOx

In this work, hafnium oxide layer is investigated as rear surface passivation layer for ultra-thin (550 nm) CIGS solar cells. Point contact openings in the passivation layer are realized by spin-coating potassium fluoride prior to absorber layer growth. Contacts are formed during absorber layer growth and visualized with scanning electron microscopy (SEM). To assess the passivating qualities, HfOx was applied in a metal-insulator-semiconductor (MIS) structure, and it demonstrates a low interface trap density in combination with a negative density of charges. Since we used ultra-thin devices that are ideal to probe improvements at the rear, solar cell results indicated improvements in all cell parameters by the addition of 2 nm thick HfOx passivation layer with contact openings.

Ag Nanoparticles Sheltered In2O3 Nanowire as a Capacitive MOS Memory Device

A capacitive memory effect has been reported for Ag nanoparticles (NPs) sheltered In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> nanowires (NWs) devices. To compare the performance with that of bare In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> NWs, two devices (viz. In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> NW/Ag NPs and In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> NW) were fabricated on n-Si substrate inside the electron beam (e-beam) evaporator using the double-step glancing angle deposition (GLAD) technique. The field emission scanning electron microscopy (FESEM) shows the formation of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> NWs and Ag NPs. The high-resolution transmission electron microscopy (HRTEM) shows the formation of uneven NWs and selected area electron diffraction (SAED) analysis confirmed the amorphous nature of the NWs. An averagely ~7.5 and ~9.3 fold enhanced absorption was observed in the UV region and visible region for In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> NW/Ag NPs. The modulation in current density of ~4.5 fold at +10 V and ~5.7 fold at -10 V were observed for the fabricated In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> NW/Ag NPs MOS device. At 2 MHz frequency response, the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> NW/Ag NPs device depicted a low interface trap density (Dit) of ~0.2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . The maximum memory window of 5.61 V at ±8 V was extracted for the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> NW/Ag NPs device from the large C-V hysteresis curve, thus establishing a strong presence of memory window in the device.

High-pressure microwave plasma oxidation of 4H-SiC with low interface trap density

Microwave plasma oxidation under a relatively high pressure (6 kPa) region is developed to rapidly grow a high-quality SiO2 layer on 4H-SiC, based on a thermodynamic analysis of SiC oxidation. By optimizing the plasma power, an atomically flat interface is achieved, and the interface trap density is lower than that of standard 1300 °C thermal-oxidized and 1350 °C NO-annealed samples measured by various methods under multiple temperature conditions. Moreover, the oxide breakdown field is higher than 9.3 MV/cm, which is comparable to that of a sample produced by high-temperature thermal oxidation. Particularly, the results of electron energy loss spectroscopy show that the transition layer between 4H-SiC and SiO2 is lower than 2 nm, indicating that microwave plasma oxidation can greatly suppress the formation of interface defects. The results strongly demonstrate the effectiveness of high-pressure plasma oxidation for SiC.

Negative Fermi-Level Pinning Effect of Metal/n-GaAs(001) Junction Induced by a Graphene Interlayer.

It is demonstrated that the electric dipole layer due to the overlapping of electron wave functions at the metal/graphene contact results in a negative Fermi-level pinning effect on the region of the GaAs surface with low interface-trap density in the metal/graphene/n-GaAs(001) junction. The graphene interlayer plays the role of a diffusion barrier, preventing the atomic intermixing at the interface and preserving the low interface-trap density region. The negative Fermi-level pinning effect is supported by the decrease of the Schottky barrier with the increase of the metal work function. Our work shows that the graphene interlayer can invert the effective work function of the metal between high and low, making it possible to form both Schottky and Ohmic-like contacts with identical (particularly high work function) metal electrodes on a semiconductor substrate possessing low surface-state density.

Extreme Temperature Operation of Ultra-Wide Bandgap AlGaN High Electron Mobility Transistors

High Aluminum content channel (Al0.85Ga0.15N/ Al0.7Ga0.3N) High Electron Mobility Transistors (HEMTs) were operated from room temperature to 500°C in ambient. The devices exhibited only moderate reduction, 58%, in on-state forward current. Gate lag measurements at 100 kHz and 10% duty only showed a slight reduction in pulsed current from DC at 500°C and high gate voltages. Interfacial trap densities were $2 \times 10^{11}$ over the range 25–300°C and $3 \times 10^{12}$ cm $^{-2}$ from 300–500°C from the subthreshold swing. These low interfacial trap densities and the near ideal gate lag measurement indicate high-quality epi layers. The insulating properties of the barrier layer led to low gate induced drain leakage current of $\sim 10^{-12}$ A/mm and $\sim 10^{-8}$ A/mm at 25 and 500°C, respectively. Low leakage current was enabled by the high Schottky barrier of the Ni/Au gate, 1.1 eV and 3.3 eV at 25 and 500°C, respectively. These properties of the AlGaN channel HEMTs demonstrate their potential for high power and high temperature operation.

Quantum Multibody Interactions in Halide-Assisted Vapor-Synthesized Monolayer WSe2 and Its Integration in a High Responsivity Photodetector with Low-Interface Trap Density

Among the two-dimensional (2D) transitional-metal dichalcogenides, monolayer (1L) tungsten diselenide (WSe2) has recently attracted a great deal of interest because of its direct band gap and tunab...