Temperature-dependent study of slow traps generation mechanism in HfO2/GeON/Ge(1 1 0) metal oxide semiconductor devices

Abstract

The lower mobility for p-type Ge based is always an issue due to slow traps generation at the interface of the metal oxide semiconductor (MOS) device which designates the defects in films generated during the deposition process. One of the effective ways to reduce this slow traps generation is to perform post deposition annealing (PDA) at a certain temperature. However, the selection of proper annealing temperature is the key to reduce defects without damaging the film quality. The effect of different PDA temperatures on the slow traps generation mechanism in the GeON passivated Ge MOS device was examined in this work. The XPS spectra show the stable formation of GeON over Ge, while HRTEM does not show any effect of PDA at the interface of GeON/Ge. The slow trap density (ΔNst) in HfO2/GeON/Ge interface annealed at different temperatures was evaluated from the hysteresis curve of C-V sweep as the function of the effective oxide field. The lowest ΔNst (4.01 × 1012 cm−2) was observed for the PDA temperature for 400 ℃. While, ΔNst increased slightly after PDA at 450 ℃. The work suggests that PDA at lower temperatures is essential to realize the high quality interface with lower interface trap density, enhanced mobility and lower CET in Ge based MOS devices. Further, it also helps to reduce the slow traps generations at the interface.