An Interface-Induced Dielectric Properties Degradation in Heterogeneous Stacked Device With P(VDF-TrFE)-Based Ferroelectric Polymers

Abstract

Heterogeneous stacked electronics are one of the major topics in flexible electronics applications, which require high performances. At the same time, P(VDF-TrFE)-based polymers with unique characteristics, e.g., ferroelectric and flexible properties, also bring attention to heterogeneous stacked device applications. Since the interfacial characteristic has strong effects with performance and reliability, therefore, it becomes one of the key issues in P(VDF-TrFE)-based heterogeneous stacked devices. In this article, a mechanism of an interface trap charge-induced low-k interfacial layer was proposed and examined by experimental methods. To analyze the low-k interfacial layer effects, both general-doping (few 1015 cm−3) p-type and n-type silicon substrate were used. These experimental results showed that different types of silicon substrates have distinct interface properties. Then, different interface trap density ( $1.75\times 10^{12}$ – $4.1\times 10^{11}$ eV−1 cm−2) silicon substrates were fabricated to further analyze the low-k interfacial layer. These showed the substrate with the lowest interface trap density has less low-k interfacial effect than other substrates do. Based on these experimental verifications, the mechanism of interface trap charge-induced low-k interface characteristic was proposed. As a consequence, this interface trap–charge-induced behavior is a necessary consideration for applications of heterogeneous stacked devices.