Low Gate Research Articles

Design and analysis of asymmetrical low-k source side spacer halo doped nanowire metal oxide semiconductor field effect transistor

In this paper, we propose a low-k source side asymmetrical spacer halo-doped nanowire metal oxide semiconductor field effect transistor (MOSFET) design and analysis. High-k spacer materials are now being researched extensively for improving electrostatic control and suppressing short-channel effects in nanoscaled electronics. However, the high-k spacers' excessive increase in fringe capacitance degrades the dynamic circuit performance. Surprisingly, this approach achieves a significant reduction in gate capacitance by maximizing the use of high-k spacer material. Three different structures, symmetrical dual-k spacer, low-k drain side asymmetrical spacer, low-k source side asymmetrical spacer halo doped nanowire MOSFET architectures are simulated and among them low-k source side asymmetrical spacer halo doped nanowire MOSFET architecture giving lower gate capacitance. After doing 3D simulations in Silvaco technology computer-aided design (TCAD) we observed that the gate capacitance and intrinsic delay are 1.23x10<sup>-17</sup> farads and 1.11x10<sup>-12</sup> seconds respectively for low-k source side asymmetrical spacer architecture and these are less as compared to high-k spacer architecture. So, the proposed structure is highly recommended for digital applications.

Novel approach for implementing ternary value logic devices showing negative differential transconductance characteristics by Fowler–Nordheim tunneling

Ternary value logic (TVL) devices are gaining attention owing to the limitations of binary devices in handling the increasing amount of information. However, the development of ternary devices has been hindered by the complex structures and use of materials lacking CMOS compatibility. This study presents a novel approach to develop ultra-simple TVL devices using thin-tunnel gate dielectrics of AlOx films and TiO2 channel layer. TVL devices are obtained by employing TiO2-based transistors with AlOx films as an oxide tunneling dielectric layer. The device exhibits typical transistor switching characteristics at low gate voltage (VG) and negative differential transconductance owing to Fowler−Nordheim tunneling current at high VG. The reversible implementation of three states, namely, ON, intermediate (INT), and OFF, with the same probability, is demonstrated with excellent reproducibility even after 200 cycles. A circuit is constructed to demonstrate the three output voltage states with respect to the input voltage by connecting the TVL device to a resistor. Additionally, the value and width of the plateau region of the INT output voltage state can be tuned by adjusting the variable resistance values. These highly simplistic TVL devices have the potential for application in low-power, highly integrated, and ultra-miniature electronic devices, thanks to their high level of CMOS compatibility.

A Voltage-Tuned Terahertz Absorber Based on MoS2/Graphene Nanoribbon Structure.

Terahertz frequency has promising applications in communication, security scanning, medical imaging, and industry. THz absorbers are one of the required components for future THz applications. However, nowadays, obtaining a high absorption, simple structure, and ultrathin absorber is a challenge. In this work, we present a thin THz absorber that can be easily tuned through the whole THz range (0.1-10 THz) by applying a low gate voltage (<1 V). The structure is based on cheap and abundant materials (MoS2/graphene). Nanoribbons of MoS2/graphene heterostructure are laid over a SiO2 substrate with an applied vertical gate voltage. The computational model shows that we can achieve an absorptance of approximately 50% of the incident light. The absorptance frequency can be tuned through varying the structure and the substrate dimensions, where the nanoribbon width can be varied approximately from 90 nm to 300 nm, while still covering the whole THz range. The structure performance is not affected by high temperatures (500 K and above), so it is thermally stable. The proposed structure represents a low-voltage, easily tunable, low-cost, and small-size THz absorber that can be used in imaging and detection. It is an alternative to expensive THz metamaterial-based absorbers.

Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET

This manuscript exclusively addresses the reliability concern of a double-drain vertical TFET (DD-VTFET) by analysing the influence of interface trap charges and variation in ambient temperature on various DC and analog/RF figure of merits. For detailed analysis, performance of the device is evaluated by considering different densities and polarities of trap charges existing at gate-oxide/channel interface. TCAD-based simulation results reveal that trap charges significantly alter the flat-band voltage, which further causes variation in the device performance. It is observed from the transfer characteristic curve that the leakage current is degraded from 10−18 to 10−13A/μm when a positive (donor) charge density of 1013 cm−2 is introduced at oxide/channel interface. However, cut-off frequency is found to be improved under the influence of donor traps, which is mainly attributed due to improvement in transconductance of the device. Moreover, simulation results indicate that DD-VTFET is immune to the negative (acceptor) traps in comparison with the positive traps. Furthermore, the analysis carried out for temperature affectability on the device performance suggests that, at higher ambient temperature, the off-state current degrades more in subthreshold region (at low gate bias) due to dominance of the Shockley-Read-Hall (SRH) and trap-assisted tunneling (TAT) mechanisms, which exponentially depend on the temperature. Therefore, the leakage current increases approximately by an order 7 when temperature is increased from 200 K to 400 K. Since band-to-band tunneling starts dominating over SRH and TAT in the super-threshold region (at high gate bias), the impact of temperature variation along with presence of the trap charges is found to be insignificant on the transfer characteristics.

Pore residues of transient receptor potential channels canonical 1 and 4 heteromer determine channel properties.

Transient receptor potential channels canonical 1 and 4 (TRPC1 and TRPC4) are proteins belonging to the same TRPC channel family, and the two are known to form a heterotetrameric channel. TRPC4 can form a homotetrameric, nonselective cation channel by itself, but the involvement of the TRPC1 subunit changes several major characteristics of the channel. In this study, we focused on the pore region (selectivity filter, pore helix, and S6 helix) of TRPC1 and TRPC4 as a determinant of the identity and characteristics of a heteromeric TRPC1/4 channel: decreased calcium permeability of the channel and outward-rectifying current-voltage (I-V) curve. Mutants and chimeras of the pore residues were created, and their currents were recorded using whole cell patch clamp. The lower gate mutants of TRPC4 exhibited diminished calcium permeability as measured by GCaMP6 fluorescence. Also, chimeric channels substituting the pore region of TRPC1 to TRPC4 were made to locate the pore region that is critical in the production of an outward-rectifying I-V curve characteristic of TRPC1/4 heteromeric channels.NEW & NOTEWORTHY Heteromer research has been a challenging field due to lack of structural studies. Using chimeras and single mutants, we present evidence that the pore region of TRPC1/4 heteromer contributes to determining the channel's characteristics such as calcium permeability, I-V curve, and conductance.

Complexity of Implementing Trotter Steps

Quantum dynamics can be simulated on a quantum computer by exponentiating elementary terms from the Hamiltonian in a sequential manner. However, such an implementation of Trotter steps has gate complexity depending on the total Hamiltonian term number, comparing unfavorably to algorithms using more advanced techniques. We develop methods to perform faster Trotter steps with complexity sublinear in the number of terms. We achieve this for a class of Hamiltonians whose interaction strength decays with distance according to power law. Our methods include one based on a recursive block encoding and one based on an average-cost simulation, overcoming the normalization-factor barrier of these advanced quantum simulation techniques. We also realize faster Trotter steps when certain blocks of Hamiltonian coefficients have low rank. Combining with a tighter error analysis, we show that it suffices to use $\left(\eta^{1/3}n^{1/3}+\frac{n^{2/3}}{\eta^{2/3}}\right)n^{1+o(1)}$ gates to simulate uniform electron gas with $n$ spin orbitals and $\eta$ electrons in second quantization in real space, asymptotically improving over the best previous work. We obtain an analogous result when the external potential of nuclei is introduced under the Born-Oppenheimer approximation. We prove a circuit lower bound when the Hamiltonian coefficients take a continuum range of values, showing that generic $n$-qubit $2$-local Hamiltonians with commuting terms require at least $\Omega(n^2)$ gates to evolve with accuracy $\epsilon=\Omega(1/poly(n))$ for time $t=\Omega(\epsilon)$. Our proof is based on a gate-efficient reduction from the approximate synthesis of diagonal unitaries within the Hamming weight-$2$ subspace, which may be of independent interest. Our result thus suggests the use of Hamiltonian structural properties as both necessary and sufficient to implement Trotter steps with lower gate complexity.

High-efficient and gate-tunable spin transport in GaN thin film at room temperature

The emerging semiconductor spintronics has offered a practical routine for developing high-speed and energy-efficient electronic and optoelectronic devices. GaN holds broad prospects for room-temperature spintronic applications due to its weak spin scattering and moderate spin–orbit coupling. However, the development of GaN-based spintronic devices is still hindered by the relatively low spin injection efficiency and gate controllability. In this study, gate-modulated spin transport was achieved in a highly spin-polarized GaN-based non-local spin valve. A maximum spin diffusion length of 510 nm and a high spin polarization of 14.1% was obtained with the CoFeB/MgO tunnel spin injector. By applying gate voltages from −3 to +3 V, the spin-dependent magnetoresistance can be tuned in the range of 1.6–3.9 Ω. The modulation is attributed to the controllable spin relaxation of electrons by the gate electric field. This work has demonstrated high spin polarization and exceptional electric controllability in GaN, pushing forward the research in spin field-effect transistors.

Scaling Study on High-Current Density Low-Dispersion GaN Vertical FinFETs

GaN vertical FinFETs on a bulk GaN substrate were fabricated with various fin widths and 400 ns pulsed I-V measurements were performed to investigate their self-heating and DC-RF dispersion. With low-temperature post-gate processes including Ar plasma-enhanced Ohmic contact, a high drain current density (>175 kA cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–2</sup> ) and a low gate leakage (<1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–7</sup> kA cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–2</sup> ) could be achieved simultaneously. When normalized by the active fin area, the specific on-resistance was 0.030mΩcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at the drain on-current of 119 kA cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–2</sup> for the 300nm fin-width single-finger device. A 25-finger device with the same fin width and fin-to-fin pitch of 3 μm showed the on-resistance of 0.043mΩcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (0.43mΩcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> when normalized by the total device area of 6000 μm2), which was one of the lowest values reported. Low DC-RF dispersion was observed for the devices more than 2.5mm away from the wafer edge. This study also reports that more influence of self-heating was observed as the fin width scaled down or the number of fingers increased.

Investigation of the Gate Degradation Induced by Forward Gate Voltage Stress in p-GaN Gate High Electron Mobility Transistors.

In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs) with Schottky-type p-GaN gate. The gate stack degradations of p-GaN gate HEMTs were investigated by performing the gate step voltage stress and the gate constant voltage stress measurements. In the gate step voltage stress test, the positive and negative shifts of threshold voltage (VTH) depended on the range of the gate stress voltage (VG.stress) at room temperature. However, the positive shift of VTH in the small gate stress voltage was not observed at 75 and 100 °C and the negative shift of VTH was started from a lower gate voltage at a high temperature compared to room temperature. In the gate constant voltage stress test, the gate leakage current increased with three steps in the off-state current characteristics as the degradation progressed. To investigate the detailed breakdown mechanism, we measured the two terminal currents (IGD and IGS) before and after the stress test. The difference between the gate-source current and the gate-drain current in the reverse gate bias indicated that the increase of the leakage current was attributed to the degradation between the gate and the source while the drain side was not affected.

Conditional permeabilization of the P. falciparum plasma membrane in infected cells links cation influx to reduced membrane integrity.

The intracellular human malaria parasite, Plasmodium falciparum, uses the PfATP4 cation pump to maintain Na+ and H+ homeostasis in parasite cytosol. PfATP4 is the target of advanced antimalarial leads, which produce many poorly understood metabolic disturbances within infected erythrocytes. Here, we expressed the mammalian ligand-gated TRPV1 ion channel at the parasite plasma membrane to study ion regulation and examine the effects of cation leak. TRPV1 expression was well-tolerated, consistent with negligible ion flux through the nonactivated channel. TRPV1 ligands produced rapid parasite death in the transfectant line at their activating concentrations, but were harmless to the wild-type parent. Activation triggered cholesterol redistribution at the parasite plasma membrane, reproducing effects of PfATP4 inhibitors and directly implicating cation dysregulation in this process. In contrast to predictions, TRPV1 activation in low Na+ media accentuated parasite killing but a PfATP4 inhibitor had unchanged efficacy. Selection of a ligand-resistant mutant revealed a previously uncharacterized G683V mutation in TRPV1 that occludes the lower channel gate, implicating reduced permeability as a mechanism for parasite resistance to antimalarials targeting ion homeostasis. Our findings provide key insights into malaria parasite ion regulation and will guide mechanism-of-action studies for advanced antimalarial leads that act at the host-pathogen interface.

A Framework for Reliability Analysis of Combinational Circuits Using Approximate Bayesian Inference

A commonly used approach to compute the error rate at the primary outputs (POs) of a circuit is to compare the fault-free and faulty copies of the circuit using XOR gates. This model results in poor accuracies with nonsampling-based methods for reliability estimation. An alternative is to use a single copy of the circuit with a four-valued representation for each net corresponding to the correct and incorrect signals. One problem in this formulation is the accurate propagation of associated probabilities. We use the framework of Bayesian inference (BI) to address this issue. We derive the conditional probability distribution (CPD) corresponding to the four-valued signals and find the output error rate using various approximate BI techniques. With our formulation, we demonstrate that the output error rate scales with the gate error probabilities. It is guaranteed to be zero when the gate error probability is zero, provided approximate BI algorithms based on sum-product belief propagation (BP) are used. Although inaccuracies increase at very low gate error probabilities, it is able to capture the relative reliability of outputs with respect to each other. We also propose a new method for finding the overall circuit error rate as the partition function for a fixed state of POs. This method provides a significant improvement in accuracy when compared with the existing method using OR gates.

Normally-Off Metal-Insulator-Semiconductor P-GaN gated AlGaN/GaN high electron mobility transistors with low gate leakage current

In this study, a normally-off AlGaN/GaN metal–insulator-semiconductor high electron mobility transistors (MIS-HEMTs) with p-GaN layer were processed, which possess a high threshold voltage and a low gate leakage current due to metal–insulator-semiconductor (MIS) gate structure. A SiNx layer as the insulator layer was deposited between p-GaN layer and gate electrode. The dependent of device performance on SiNx thickness was investigated. Moreover, the threshold voltage of normally-off MIS-HEMT was emphatically discussed with different insulator layer thickness. It demonstrates that obviously positive shifting for threshold voltage from 1.5 to 6 V was achieved by increasing the SiNx thickness from 0 to 20 nm, while the channel mobility was comparable for all samples. Besides, the introduction of MIS gate structure is also beneficial for suppressing the gate leakage current and improving the maximum gate voltage swing owing to the high breakdown field of approximately 8.3 MV/cm.

Synaptic MoS2 transistors based on charge trapping two-dimensionally confined in Sr2-xCoxNb3O10 nanosheets

Two-dimensional (2D) synaptic devices based on charge trap/de-trap have attracted much attention due to their superior characteristics that is gate tunability, large switching ratio, long-term retention, and distinct synaptic potentiation/depression with low power. Here, we introduce a 2D Sr2-xCoxNb3O10 (SCNO) nanosheet layer between the MoS2 channel and SiO2 substrate because charge trap sites confined in SCNO nanosheet layer are anticipated to precisely control the 2D channel conductance. The hysteretic and synaptic behaviors of MoS2 channel can be controlled by charge trap/de-trap in two-dimensionally confined nanosheet layer with different doping ratio of Co. As the x value for the MoS2/SCNO field effect transistor (FET) increases, the shift of the threshold voltage (Vth) in a transfer curve increases and more linear potentiation/depression curves are induced with lower gate voltage pulse. In addition, paired-pulse facilitation is successfully implemented in a MoS2/SCNO FET. Therefore, our results suggest the feasibility of improved and efficient emulation of biological synaptic behavior in MoS2 transistors in contact with 2D oxide nanosheet layer.

Hot Carrier Injection Reliability of Fabricated N- and P-Type Multi FinFETs with Different TiN Stacks

Device degradation due to hot carrier injection (HCI) in multi-fin 20 nm and 10 nm N- and P-type FinFET devices are thoroughly analyzed. To further understand the HCI reliability of the four FinFET devices, the device is fabricated with a standard Vt base and low Vt base gate stacks with different work functions. It is evident that: (i) The standard Vt device sustains lower effective stress bias due to the difference in threshold voltage, resulting in a more stable threshold voltage than the low Vt base device, and (ii) the transconductance of the single N- and P-type FinFET is more severely degraded than the multi-fin N- and P-type FinFET, mainly because multi N- and P-type Finfet has coupe effect, which effectively reduces the impact of HCI.

Low-Operating-Voltage Two-Dimensional Tin Perovskite Field-Effect Transistors with Multilayer Gate Dielectrics Based on a Fluorinated Copolymer.

The fabrication of organic-inorganic perovskite field-effect transistors (FETs) with polymer gate dielectrics is challenging because of the solvent corrosion and wettability issues at interfaces. A few polymers have been integrated into perovskite transistors; however, these devices have high operating voltages due to low dielectric constants. Herein, poly(vinylidenefluoride-co-trifluoroethylene) (PVDF-TrFE) with a high dielectric constant is introduced into bottom-gate phenylethylammonium tin iodide perovskite [(PEA)2SnI4] FETs. Polytetrafluoroethylene (PTFE) and cross-linked poly(4-vinylphenol) (PVP) (CL-PVP) are used to address the issues of solvent corrosion and wettability. We design the PVDF-TrFE/PTFE and PVDF-TrFE/PTFE/CL-PVP dielectric layers, where the ferroelectric properties of PVDF-TrFE are reduced by PTFE. The (PEA)2SnI4 FETs operate at relatively low gate voltages, exhibiting good overall performance with average hole mobilities of 0.42 and 0.36 cm2 V-1 s-1. Our findings provide a feasible strategy for constructing low-operating-voltage perovskite FETs with large-dielectric-constant ferroelectric polymers as gate dielectrics by a solution processing technique.

Recent development of economic indicators on Czech dairy farms

A reassessment of factors related to milk production economics is needed because of continuing genetic improvements within the main dairy breeds and changes in farm management and the economic environment. Therefore, in this study, we aimed to evaluate the development of economic indicators between 2016 and 2020 on Czech dairy farms that kept either Czech Fleckvieh or Holstein breeds and that had different average milk yields. We used a questionnaire to obtain data from 66 dairy farms from different regions of the Czech Republic. The farms were divided into four groups according to breed and 2016 milk yield. Production costs increased during the period in all groups by 13% to 17% because of increasing milk yields, the associated higher feed consumption and increasing input prices. We observed a higher annual growth rate of costs per litre of milk on farms with above-average milk yields compared with the groups with below-average yields. The highest profitability before subsidies was achieved on farms with Holstein cows and above-average milk yields. Higher-income over feed costs were consistently observed in groups with higher milk yields. Because of low farm gate milk prices, profitability was significantly lower across all groups during 2016 than in other years.

TCAD performance analysis of a symmetrical double gate non-aligned junction FET device with high and low dielectric gate oxide in sub-100 nm regime

ABSTRACT This paper presents 2D-Sentaurus TCAD tool results of a Non-aligned Double Gate Junction N-Channel Field Effect Transistor (NADGNFET) device; the response analysis of device to gate oxide dielectric materials, i.e. silicon dioxide (SiO2) and hafnium dioxide (HfO2), is also presented. The NADGNFET in 90 nm device length is the proposal of this work to improve the second-order effects as well transistor non-linear performance at radio frequency (RF). A non-aligned device in this work consists of two gates extending to the source and drain region with 44.44% channel overlap in total device length. As compared to a full overlap device, the present device has shown better results in Analog Figure of Merit (FOM) and RF parameters like: ION current, ION/IOFF ratio, DIBL (Drain Induced Barrier lowering), SS (Subthreshold Swing), Intrinsic gain (AVO), Transconductance Generation Factor (TGF), Transconductance Frequency Product (TFP), Cut-off frequency (fT), Intercepted Input Power-3 (IIP3) and Intermodulation Distortion power-3 (IMD3). The use of dielectric material with high dielectric constant (HfO2, k = 24) in gate oxide reduces DIBL by 50%, increases the ION/IOFF ratio by 59.1%, increases the Intrinsic gain by 50% compared to low-k dielectric constant (SiO2, k = 3.9). However, results also shows that high-frequency parameters’ results were better with low-k dielectric constant. This gives a trade-off in device application.

Gating transitions in the MthK potassium channel.

Potassium channels form one of the most ubiquitous classes of proteins and are found across all forms of life. Permeation of ions through potassium channels is controlled in different ways, most notably at the lower gate and at the selectivity filter. Here, we focus on the MthK channel, an archaeal calcium-gated potassium channel that has seen wide use as a model system. Particularly, binding of Ca2+ ions opens full-length MthK, possibly also triggering the allosteric coupling between the filter and the gate. To understand the gating behavior in more detail, we apply molecular dynamics (MD) simulations, with and without applied voltage, combined with essential dynamics sampling. This is enabled by the recent availability of both closed and open conformations.

A Suppression Method for Gate-Source Voltage Oscillation With Clamping Function for GaN Devices

Gallium nitride (GaN) devices are generally more prone to severe switching oscillations than Si <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfets</small> due to their fast switching speeds. Different from Si and SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfets</small> , GaN devices typically have a lower maximum gate voltage rating. Taking the Efficient Power Conversion Corporation series as an example, the gate drive voltage is usually 5 V, but the maximum voltage rating is 6 V. Therefore, GaN devices are more susceptible to damage from gate-source voltage oscillation. In this letter, a gate drive circuit with a clamping function is proposed to suppress gate-source voltage oscillation. The adopted method can not only clamp the gate voltage of the GaN device near the drive voltage to protect the device, but also does not affect the switching speed of the device. The proposed method mainly uses some passive components that make the circuit design simpler compared with other active gate driver methods. Finally, the effectiveness of the proposed method is verified by experiments.

Electrophysiological properties of TRPC1/4 heteromer determined by its pore residues.

Transient receptor potential canonical 1 (TRPC1) is widely expressed in various mammalian tissues and is involved in many physiological functions. It is known to heteromerize with TRPC4 to form a cationic channel, and it induces significant changes in channel characteristics. The huge differences in channel characteristics in the physiological environment indicates the importance of channel regulation in many tissues expressing both TRPC1 and TRPC4. In this study, we focused on the pore region (selectivity filter, pore helix, and S6 helix) of TRPC1 and TRPC4, compared their homology, and investigated how they contribute to the electrophysiological characteristics of the ion channel. We observed changes in G-V curve and I-V curve with mutations of the pore region and demonstrated that TRPC4 selectivity filter mutants lost sensitivity to G protein mediated activation. Moreover, lower gate mutants of TRPC4 exhibited diminished calcium permeability compared to wild type channels. Through chimeric channels where we substituted the pore region of TRPC1 with that of TRPC4, we were able to determine regions that are critical in producing the double-rectifying I-V curve of the homomeric TRPC4 channel.