Low Gate Research Articles

An Ultralow-Power Real-Time Machine Learning Based fNIRS Motion Artifacts Detection.

Due to iterative matrix multiplications or gradient computations, machine learning modules often require a large amount of processing power and memory. As a result, they are often not feasible for use in wearable devices, which have limited processing power and memory. In this study, we propose an ultralow-power and real-time machine learning-based motion artifact detection module for functional near-infrared spectroscopy (fNIRS) systems. We achieved a high classification accuracy of 97.42%, low field-programmable gate array (FPGA) resource utilization of 38354 lookup tables and 6024 flip-flops, as well as low power consumption of 0.021 W in dynamic power. These results outperform conventional CPU support vector machine (SVM) methods and other state-of-the-art SVM implementations. This study has demonstrated that an FPGA-based fNIRS motion artifact classifier can be exploited while meeting low power and resource constraints, which are crucial in embedded hardware systems while keeping high classification accuracy.

Memory-Based Self-Ordering FFT for Efficient I/O Scheduling

A complex-valued self-ordering radix-2 memory-based Fast Fourier Transform (FFT) architecture suitable for low end Field Programmable Gate Arrays (FPGA) is presented. Employing a self-ordering algorithm within the data flow, both input and output data are kept in normal sequential order, not in digit-reversed-order. This way, with an appropriate scheduling, last stage of the FFT and I/O operations are performed in parallel with no wait states. Self-ordering FFT algorithms are generally designed for software implementations. We designed and implemented one on FPGA (hardware), showing that considerable number of clock cycle savings can be obtained compared to unordered FFT counterparts. The approach is implemented on various FPGAs. The results are compared with similar radix-2 architectures in terms of required clock cycles and resource usage, confirming the advantage of the approach.

Phosphatidylinositol-4,5-biphosphate (PIP2)-Dependent Thermoring Basis for Cold-Sensing of the Transient Receptor Potential Melastatin-8 (TRPM8) Biothermometer

The menthol sensor transient receptor potential melastatin-8 (TRPM8) can be activated by cold and, thus, serves as a biothermometer in a primary afferent sensory neuron for innocuous-to-noxious cold detection. However, the precise structural origins of specific temperature thresholds and sensitivity have remained elusive. Here, a grid thermodynamic model was employed, to examine if the temperature-dependent noncovalent interactions found in the 3-dimensional (3D) structures of thermo-gated TRPM8 could assemble into a well-organized fluidic grid-like mesh network, featuring the constrained grids as the thermorings for cold-sensing in response to PIP2, Ca2+ and chemical agents. The results showed that the different interactions of TRPM8 with PIP2 during the thermal incubation induced the formation of the biggest grids with distinct melting temperature threshold ranges. Further, the overlapped threshold ranges between open and pre-open closed states were required for initial cold activation with the matched thermo-sensitivity and the decrease in the systematic thermal instability. Finally, the intact anchor grid near the lower gate was important for channel opening with the active selectivity filter. Thus, PIP2-dependent thermorings in TRPM8 may play a pivotal role in cold sensing.

Characterization of larger-single-Lorentzian noise deviated from 1/f characteristics detected by a power-spectral-density-integration method

Larger-single-Lorentzian noise that deviates significantly from a 1/f characteristic generated by MOSFET is quantitatively analyzed using a unique evaluation method, which integrates power spectral density over a predetermined frequency band. As a result, the appearance of larger-single-Lorentzian noise is stochastically present and for low gate voltage. According to drain voltage dependence, it is suggested that the origin of larger-single-Lorentzian noise is in a pinch-off region and results from border traps in a gate oxide film by which hot carriers are trapped/de-trapped.

Assessment of temperature and ITCs on single gate L-shaped tunnel FET for low power high frequency application

In a vertical TFET structure, controllability over the gate is enhanced because of the favorable electrostatic potential and tunneling under the entire gate region by preventing the direct source to drain tunneling. For an L-shaped TFET, the Band-to-Band-Tunneling (BTBT) is perpendicular and parallel to the channel length. Also, it has a higher I on (ON-current) with suppressed ambipolar current (low I ambi ) and is more scalable than other vertical BTBT mechanism-based TFET structures. The reliability of n-type single gate L-shaped TFET (SG-nLTFET) is investigated by examining: (1) impact of temperature (Temp K ) variation (from 260 K to 460 K) and (2) Interface trap charge (ITCs) polarity at fixed charge density on analog /RF /linearity figure of merits (FOMs). The obtained results reveal that change in polarity of ITCs at the Si/HfO 2 interface,modifies the analogue characteristics of the SG-nLTFET significantly in terms of turn-on voltage as well as I on . The temperature sensitivity of SG-nLTFET device indicates that the ShockleyReadHall (SRH) and Trap-Assisted-Tunneling (TAT) phenomenon dominates at lower gate bias and degrades the I on /I off ratio at high temperatures. On the other hand, the BTBT mechanism predominates in the subthreshold regime of transfer characteristics. Furthermore, the results reveal that the off-state current (I off ) degrades dramatically at high temperatures. According to the empirical analysis, SG-nLTFET is insusceptible to Positive-ITCs (Donor trap charges, P-ITCs) present at Si/HfO 2 interface in comparison to Negative-ITCs (Acceptor trap charges, N-ITCs).

A Virtual Fabrication and High-Performance Design of 65 nm Nanocrystal Floating-Gate Transistor

Floating-gate transistor lies at the heart of many aspects of semiconductor applications such as neural networks, analog mixed-signal, neuromorphic computing, and especially in nonvolatile memories. The purpose of this paper was to design a high-performance nanocrystal floating-gate transistor in terms of a large memory window, low power, and extraordinary erasing speeds. Besides, the transistor achieves a thin thickness of the tunnel gate oxide layer. In order to obtain the high-performance design, this work proposed a set of structure parameters for the device such as the tunnel oxide layer thickness, Interpoly Dielectric (IPD), dot dimension, and dot spacing. Besides, this work was successful in the virtual fabrication process and methodology to fabricate and characterize the 65 nm nanocrystal floating-gate transistor. Regarding the results, while the fabrication process solves the limitation of the tunnel oxide layer thickness with the small value of 6 nm, the performance of the transistor has been significantly improved, such as 2.8 V of the memory window with the supply voltage of ±6 V at the control gate. In addition, the operation speeds are compatible, especially the rapid erasing speeds of 2.03 μs, 28.6 ns, and 1.6 ns when the low control gate voltages are ±9 V, ±12 V, and ±15 V, respectively.

Molecular details of ruthenium red pore block in TRPV channels.

Transient receptor potential vanilloid (TRPV) channels play a critical role in calcium homeostasis, pain sensation, immunological response, and cancer progression. TRPV channels are blocked by ruthenium red (RR), a universal pore blocker for a wide array of cation channels. Here we use cryo-electron microscopy to reveal the molecular details of RR block in TRPV2 and TRPV5, members of the two TRPV subfamilies. In TRPV2 activated by 2-aminoethoxydiphenyl borate, RR is tightly coordinated in the open selectivity filter, blocking ion flow and preventing channel inactivation. In TRPV5 activated by phosphatidylinositol 4,5-bisphosphate, RR blocks the selectivity filter and closes the lower gate through an interaction with polar residues in the pore vestibule. Together, our results provide a detailed understanding of TRPV subfamily pore block, the dynamic nature of the selectivity filter and allosteric communication between the selectivity filter and lower gate.

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

The design and performance analysis of a Si-SiGe heterostructure-based double gate feedback field-effect transistor (HDG FBFET) are presented in this paper. The proposed HDG FBFET is capable of providing high on current (3 × 10−4 A/μm) with a large I ON /I OFF ratio (3 × 1011) and is scalable up to 20 nm channel length. Its exceptionally steep switching characteristics (SS < 1 mV/decade) and ability to switch ON/OFF at lower gate voltage due to the use of smaller band-gap material (Si1−x Ge x ) in channel-2 and drain regions make it suitable for use in low power applications. A significant hysteresis window of 4.99 V is also achieved by the device, which can be extremely helpful for memory applications. Moreover, a comprehensive investigation of the nature of hysteresis in relation to the different device parameters has also been carried out. The designing of the device structure and all of the electrical performance characterization have been done using the Sentaurus TCAD tool.

Physics based model development of a double gate reverse T-shaped channel TFET including 1D and 2D band-to-band tunneling components

In this article, a Double gate reverse T-shaped channel tunnel field effect transistor (DG-RT-TFET) is mathematically modeled. The TFET has the potential for exhibiting various types of tunneling mechanisms. The modeled device encompasses both 1D and 2D Band-to-Band (BTBT) tunneling components, with each component developed in the epi-channel and channel, respectively. The study reveals that the 2D BTBT components exhibit greater dominance in the lower gate bias or subthreshold region, while the 1D BTBT becomes more prominent at higher gate bias voltages. By incorporating both models, a more comprehensive understanding of the DG-RT-TFET behavior can be achieved. To ensure the accuracy and reliability of the developed model, all model parameters are calibrated using the TCAD-sentaurus simulator. By comparing the results obtained from the developed model with the simulation results, it is concluded that the developed model for the DG-RT-TFET is suitable for capturing the device behavior and characteristics.

Analysis of Lanthanum Oxide Based Double-Gate SOI MOSFET using Monte-Carlo Process.

This work proposes a Double-Gate (DG) MOSFET with a Single Material made of Silicon On-Insulator (SOI). The Lanthanum Oxide material with a high k-dielectric constant has been used as an interface between two gates and the channel. The Monte Carlo analysis has been used to determine the Conduction Band Energy (Ec) profiles and electron sheet carrier densities (ns) for a Silicon channel thickness (tsi) of 10 nm at 0.5 V gate drain-source voltages. The transverse electric fields are weak at the midchannel of DG SOI MOSFETs, where quantum effects are encountered. The Monte Carlo simulation has been confirmed to be effective for high-energy transport. A particle description reproduces the granularity property of the transport for nanoscale modeling. This work utilizes a Monte Carlo (MC) Simulation for the proposed Double Gate Single Material Silicon On Insulator MOSFET with (La2O3=2 nm) as dielectric oxide on upper and lower gate material. The electrical properties of the DG SOI MOSFETs with Lanthanum Oxide were analyzed using Monte Carlo simulation, including the conduction band energy, electric field, potential distribution, particle movement, and average velocity. The peak electric field (E) simulation results and an average drift velocity (υavg) of 6Í105 V/cm and 1.6Í107 cm/s were obtained, respectively. The conduction band energy for the operating region of the source has been observed to be 4 % to the drain side, which obtained a value of -0.04 eV at the terminal end. This proposed patent design, such as double-gate SOI-based devices, is the best suggestion for significant scalability challenges. Emerging technologies reach the typical DG SOI MOSFET's threshold performance when their geometrical dimensions are in the nanometer region. This device based on nanomaterial compounds has been more submissive than conventional devices. The nanomaterials usage in the design is more suitable for downscaling and reducing packaging density.

Nonlinear frequency modulation for Fourier transform ion mobility mass spectrometry improves experimental efficiency

Through optimization of terminal frequencies and effective sampling rates, we have developed nonlinear sawtooth-shaped frequency sweeps for efficient Fourier transform ion mobility mass spectrometry (FT-IM-MS) experiments. This is in contrast to conventional FT-IM-MS experiments where ion gates are modulated according to a linear frequency sweep. Linear frequency sweeps are effective but can be hindered by the amount of useful signal obtained using a single sweep over a large frequency range imposed by ion gating inefficiencies, particularly small ion packets, and gate depletion. These negative factors are direct consequences of the inherently low gate pulse widths of high-frequency ion gating events, placing an upper bound on FT-IM-MS performance. Here, we report alternative ion modulation strategies. Sawtooth frequency sweeps may be constructed for the purpose of either extending high-SNR transients or conducting efficient signal-averaging experiments for low-SNR transients. The data obtained using this approach show high-SNR signals for a set of low-mass tetraalkylammonium salts (<1000 m/z) where resolving powers in excess of 500 are achieved. Data for low-SNR obtained for multimeric protein complexes streptavidin (53 kDa) and GroEL (800 kDa) also reveal large increases in the signal-to-noise ratio for reconstructed arrival time distributions.

Low Turn-Off Loss Lateral Insulated Gate Bipolar Transistor With Double Deep P-Regions

Low Turn-Off Loss Lateral Insulated Gate Bipolar Transistor With Double Deep P-Regions

Analysis and modeling of reverse-biased gate leakage current in AlGaN/GaN high electron mobility transistors

We have analyzed and modeled the reverse-biased gate leakage current in a Schottky-gate AlGaN/GaN high electron mobility transistor. While the Poole–Frenkel emission current along conductive threading dislocations dominates at low negative gate bias, the trap-assisted tunneling of thermally energized electrons and the thermal emission of electrons from threading dislocations aided by dislocation-related states at multiple energy levels within the AlGaN bandgap are dominant at moderate to large reverse bias. Additionally, deep trap levels of high density localized near the gate/AlGaN interface cause significant leakage at 473 K at low to moderate reverse bias, which could be specific to the device we have analyzed. We extracted about 1012 cm−2 traps near the AlGaN/GaN interface from the difference of the barrier layer electric field profile obtained from the experimental high-frequency capacitance–gate voltage and the one needed for final matching. The thermionic- and the thermionic field-emission currents are considerably low; the latter, however, dominates in the defect-free case. Finally, the simulation framework we developed here helped us identify various conduction mechanisms contributing to the reverse-biased gate leakage and the density and electronic structure of the responsible defects.

Novel T-Shaped Gate Structure of AlGaN/GaN HEMTs on Si for RF Application

Due to the high electron saturation velocity and breakdown electric field, GaN-based high electron mobility transistors (HEMTs) have been widely used in high frequency and power application, such as telecommunication, satellite communication, and radar system [1]. Since first demonstration of AlGaN/GaN HEMTs in 1993 [2], the RF performance of these device has continuously improved by the progress on epitaxy and device scaling technology [3].The current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) from the small-signal equivalent circuit of the HEMT are derived by the following equations [4].From these equations, it can be concluded that in order to achieve high frequency operation, HEMTs should be designed with a T-shaped gate structure that simultaneously achieves low gate resistance (Rg) and low parasitic capacitance (Cgs and Cgd). However, there are complex fabrication processes to form the T-shaped gate. Typically, the T-shaped gate structure is implemented through electron beam lithography process using a tri-layer resist such as PMMA/PMGI/PMMA, which requires multiple exposures or developments. Multiple exposures can cause overlay errors that can significantly affect the T-shaped gate with smaller gate lengths [5]. Also, it is difficult to obtain an undercut structure that enables a good lift-off and guarantees a high yield due to the need for precise dose control. In addition, since the T-shaped gate has an unstable structure in which a narrow foot supports the weight of a wide head, the gate may collapse during a subsequent process.In this work, we fabricated a novel T-shaped gate using the negative e-beam resist HSQ, which offers a simple T-shaped gate fabrication process. The HSQ that was exposed to e-beam is located underneath the gate head and on both sides of the gate foot in our novel T-shaped gate design, providing a robust structure. The HSQ-assisted gate HEMTs exhibit comparable DC/RF performance compared to conventional T-shaped gate HEMTs. Acknowledgement This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MIST) (No. NRF-2021M3C13097672).

Simulation study of multi-source hetero-junction TFET-based capacitor less 1T DRAM for low power applications

A capacitorless one-transistor dynamic random access memory (1T DRAM) based on multi-source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The analysis of the three memory functions: Write, Hold and Read of 1T DRAM has been carried out using Synopsys TCAD simulations. A storage region of Ge material is used for the accumulation of holes/to store the charge carriers. The variation in length of Ge-storage region, under lap length (Lunder), and temperature is performed to analyse the DRAM performance. In the Write operation, the tunneling window reduces to 15 nm and holes can be easily stored in the Ge-storage region. In case of Hold1 and Read1 operations, the potential barriers are reduced by 0.24 eV, and 0.1 eV respectively. In the proposed multi-source TFET with 14 nm gate length, read current ratio i.e. IR1/IR0 of 4.4, retention time (RT) greater than 10 sec, and sense margin (SM) of 1.27 × 10−6 A/µm is achieved at room temperature. The proposed multi-source TFET based 1T DRAM is operating at very low gate voltages. Therefore, this device is well suited for low power applications.

Gate leakage suppression of normally-OFF diamond FET by employing MOS-MES hybrid gate structure

Normally-off filed-effect transistors (FETs) are critical for logical circuit and switch systems. However, the presence of two-dimensional holes in hydrogen-terminated diamond (CH diamond) makes most of regular CH diamond MOSFETs normally-ON operation, leading to energy loss. Metal-semiconductor (MES) FETs with Schottky gate are a good way to achieve normally-off CH diamond FETs, but have the disadvantage of high gate leakage current. In this work, a MOS-MES hybrid gate diamond FET with normally-off operation and low gate leakage current was fabricated by adding nanoparticles Al2O3 (nano-Al2O3) between Al/C-H diamond interface. The MES formed by Al/C-H diamond plays the role of realizing normally-off operation, and the MOS of Al/nano-Al2O3/C-H diamond is used to lower the gate leakage current. 100 % of hybrid gate devices displayed normally-off operation with threshold voltages ranging from −0.2 V to −1.2 V, as well as the gate leakage current is 103-106-fold lower than that of FET without nano-Al2O3. The hybrid gate structure is poised to become a part of the FET community.

Reconfigurable Feedback Field-Effect Transistors with a Single Gate.

In this study, we present a reconfigurable feedback field-effect transistor (FET) that can operate in both p- and n-type configurations using a feedback mechanism. In contrast to previously reported reconfigurable FETs, our device utilizes a single gate to trigger a feedback mechanism at the center, resulting in steep switching characteristics. The device exhibited high symmetry of transfer characteristics, an on/off current ratio of approximately 1010, extremely low subthreshold swings, and a high on-current of approximately 1.5 mA at low gate voltages in both configurations. In addition, because of their hysteresis and bistable characteristics, they can be applied to various electronic devices. These characteristics were analyzed using a commercial device simulator.

Ionic liquid gating of YBa2Cu3O7−x with a BN capping layer for enhanced stability and efficiency

In this study, we explored the impact of ionic liquid gating on YBa2Cu3O7−x superconductivity. We observed that direct contact of YBa2Cu3O7−x and the ionic liquid N-diethyl-N-methyl-N-(2methoxyethyl)ammonium bis(trifluoromethanesulfonyl)imide (DEME-TFSI) results in irreversible electrochemical reactions, despite the application of a relatively low gate voltage at 220 K. Capping a thin layer of boron nitride (BN) on YBa2Cu3O7−x enabled a reversible modulation of carrier density at 300 K. Benefiting from the higher ion mobility of ionic liquid at 300 K, this modification led to more than a one-time increase in carrier density, a 3-time improvement in voltage modulation efficiency, and a reversible tuning of the superconducting temperature. These findings suggest that using a BN capping layer holds promise for enhancing the stability and efficiency of devices using ionic liquid gating.

Local mapping of surface potential in pentacene thin film under gate bias voltage obtained by scanning kelvin probe microscopy.

We report the local surface potential mapping of pentacene film prepared by physical vapor deposition with scanning kelvin probe microscopy where the sample is scanned under different gate voltages. Surface topography and the corresponding potential maps were obtained simultaneously. Spatial distribution of the surface potential at a low gate voltage is clearly correlated with topographic features. A lower electrostatic potential was measured at the grain boundaries (GBs), suggesting that GBs behave as hole traps. This observation is bolstered by conductive atomic force microscopy (C-AFM) data, which reveals a higher conductivity within the grains as opposed to the GBs. An increase in gate voltage minimizes the potential differences at the grain and GBs, suggesting a modification in trap occupancy. We expect that these experimental results, along with existing theories, will provide a better understanding of the microstructural-electrical properties of pentacene film. RESEARCH HIGHLIGHTS: Local surface potential mapping of pentacene film with scanning kelvin probe microscopy. Correlation between the surface potential map and topography at a low gate voltage. Decrease of the potential distribution inhomogeneity by the gate voltage increasement. Higher conductivity at inner grain than grain boundary in conductive atomic force microscopy.

Comparative Study on Indium Precursors for Plasma-Enhanced Atomic Layer Deposition of In2O3 and Application to High-Performance Field-Effect Transistors.

Indium oxide (In2O3) is a transparent wide-bandgap semiconductor suitable for use in the back-end-of-line-compatible channel layers of heterogeneous monolithic three-dimensional (M3D) devices. The structural, chemical, and electrical properties of In2O3 films deposited by plasma-enhanced atomic layer deposition (PEALD) were examined using two different liquid-based precursors: (3-(dimethylamino)propyl)-dimethyl indium (DADI) and (N,N-dimethylbutylamine)trimethylindium (DATI). DATI-derived In2O3 films had higher growth per cycle (GPC), superior crystallinity, and low defect density compared with DADI-derived In2O3 films. Density functional theory calculations revealed that the structure of DATI can exhibit less steric hindrance compared with that of DADI, explaining the superior physical and electrical properties of the DATI-derived In2O3 film. DATI-derived In2O3 field-effect transistors (FETs) exhibited unprecedented performance, showcasing a high field-effect mobility of 115.8 cm2/(V s), a threshold voltage of -0.12 V, and a low subthreshold gate swing value of <70 mV/decade. These results were achieved by employing a 10-nm-thick HfO2 gate dielectric layer with an effective oxide thickness of 3.9 nm. Both DADI and DATI-derived In2O3 FET devices exhibited remarkable stability under bias stress conditions due to a high-quality In2O3 channel layer, good gate dielectric/channel interface matching, and a suitable passivation layer. These findings underscore the potential of ALD In2O3 films as promising materials for upper-layer channels in the next generation of M3D devices.