Low Gate Leakage Current Research Articles

Electrical properties of HfTiON gate-dielectric metal-oxide-semiconductor capacitors with different Si-surface nitridations

Electrical properties of HfTiON gate-dielectric metal-oxide-semiconductor (MOS) capacitors with different Si-surface nitridations in N2O, NO, and NH3 prior to high-k film deposition are investigated and compared. It is found that the NO-nitrided sample exhibits low interface-state density and gate leakage current, and high reliability. This is attributed to formation of a SiON interlayer with suitable proportions of N and O. The MOS capacitor with Hf0.4Ti0.6OxNy∕SiON gate dielectric stack (capacitance equivalent thickness of 1.52nm and k value of 18.9) prepared by NO surface nitridation has an interface-state density of 1.22×1011cm−2eV−1 and gate leakage current density of 6×10−4Acm−2 (Vg=1V). Moreover, only a small degradation of electrical properties after a stressing at 10MV∕cm for 3000s is observed for the NO-nitrided sample.

Field emission devices for advanced electronics comprised of lateral nanodiamond or carbon nanotube emitters

Nanocarbon-derived electron emission devices, specifically, nanodiamond lateral field emission diodes and gated carbon nanotube triodes are new configurations for robust nanoelectronic devices. These novel micro/nanostructures provide an alternative and efficient means of accomplishing electronics that are impervious to temperature and radiation. Nitrogen-incorporated nanocrystalline diamond has been lithographically micropatterned to utilize the material as an electron field emitter. Arrays of laterally arranged “finger-like” nanodiamond emitters constitute the cathode in a versatile diode configuration with small interelectrode separation. Nanodiamond lateral tip conditioning techniques are employed to improve emission and the subsequent device performance discussed. A low diode turn-on voltage of 7 V and a high emission current of 90 μA at an anode voltage of 70 V (electric field of ∼ 7 V/μm) is reported for the nanodiamond lateral device. Also, the development of a field emission triode amplifier based on aligned carbon nanotubes (CNTs) with low turn-on voltage and small gate leakage current, utilizing a dual-mask microfabrication process is reported. The2 × 20 μm CNT triode array displays a gate turn-on voltage of ∼ 44 V, and low gate currents less than 3% of the anode currents. The low gate leakage currents observed confirmed the effectiveness of the convex-shaped gated CNT emitter in alleviating the cathode-gate leakage problem that compromises the operation of a field emission triode.

Characterization of AlGaN/GaN MOSHFETs with Al2O3 as gate oxide

AbstractWe report on AlGaN/GaN metal‐oxide‐semiconductor heterostructure field‐effect transistors (MOSHFETs) with MOCVD deposited Al2O3 as a gate oxide. Properties of MOSHFETs with 9 nm and 14 nm thick Al2O3 are compared with conventional HFETs prepared simultaneously on the same layer structure. Lower gate leakage current (∼10–5 A/mm at –10 V) and higher saturated drain current (up to 40%) are obtained for MOSHFETs than those for HFETs. In contradiction to previously reported data, the extrinsic transconductance for MOSHFETs is also higher (up to 37% of peak values) than that for HFET. This indicates on semi‐conductive rather than insulating properties of Al2O3 gate oxide. Pulsed I–V measurements (pulse width 1 µs) yielded lower but still measurable current collapse in MOSHFETs compared to HFETs. Nevertheless, obtained results show that Al2O3 gate oxide, after optimising its microstructure and thickness, can be preferable for the preparation of AlGaN/GaN MOSHFETs. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Origin and elimination method of parasitic gate leakage current for AlGaN/GaN heterostructure field effect transistor

The Schottky gate leakage current of AlGaN/GaN HFET was systematically investigated. Experimental results were acquired from gates of HFET and from round diodes on the same wafer. The performed analysis clearly shows that HFET gate current behaves according to additional physical mechanism. Hypothesis, that the source of parasitic leakage is the contact point between gate metal and two dimensional electron gas on the mesa edges, was theoretically and experimentally proved. Cost effective technological solution with SiO2 “patch” layer is presented. Transistors, manufactured with “patch” layer, have higher breakdown, two orders of magnitude lower gate leakage current, excellent performance and should be more reliable. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

0.6nm-EOT high-k gate stacks with HfSiO x interfacial layer grown by solid-phase reaction between HfO 2 and Si substrate

We have developed a process for forming an ultra-thin HfSiO x interfacial layer (HfSiO x-IL) for high-k gate stacks. The HfSiO x-IL was grown by the solid-phase reaction between HfO 2 and Si-substrate performed by repeating the sequence of ALD HfO 2 deposition and RTA. The HfSiO x-IL grown by this method enables the formation of very uniform films consisting of a few mono-layers, and the dielectric constant of the HfSiO x-IL is about 7. The FUSI-NiSi/HfO 2 gate stacks with HfSiO x-IL have achieved 0.6 nm EOT, a very low gate leakage currents between 1 A/cm 2 and 5 × 10 −2 A/cm 2, an excellent subthreshold swing of 66mV/dec, and a high peak mobility of 160 cm 2/Vs compared to the reference samples without HfSiO x-IL. These results indicate that the HfSiO x-IL has a good quality compared to the SiO 2 interfacial layer grown by oxygen diffusion through HfO 2 films.

Organic field-effect transistors and memory elements using deoxyribonucleic acid (DNA) gate dielectric

Deoxyribonucleic acid (DNA) bio-polymers derived from fish waste products are employed as gate dielectric in n-type methanofullerene as well as p-type pentacene based organic field-effect transistors working at low voltage levels and low gate leakage currents. Based on the large hysteresis in the transfer characteristics, operation of the transistor as a non-volatile memory element is shown. Practically hysteresis free operation of DNA based transistors is obtained at low voltage levels by adding an additional aluminium oxide blocking layer between the organic semiconductor and the DNA gate dielectric.

P‐5: Solution‐Processed SiO2 Films Using Hydrogenated Polysilane Based Liquid Materials

AbstractPolycrystalline silicon thin‐film transistors (poly‐Si TFTs) have been fabricated using solution‐processed SiO2 films made from a polysilane‐based liquid precursor. Spin‐coating this precursor, which already had been reported as a precursor for silicon film [Nature, vol. 440, pp. 783–786, 2006], we have prepared gate silicon oxide films for the TFTs. The fabricated TFT has been operated with the mobility of 108.9 cm2/Vs and sufficient low gate leakage current.

Suppressed growth of unstable low-k GeOx interlayer in Ge metal-oxide-semiconductor capacitor with high-k gate dielectric by annealing in water vapor

The effects of water vapor added in the N2 annealing of high-k HfTiON gate dielectric on Ge metal-oxide-semiconductor capacitor are investigated. Both transmission-electron microscopy and ellipsometry indicate that, as compared to dry-N2 annealing, the wet-N2 annealing can greatly suppress the growth of unstable low-k GeOx at the dielectric/Ge interface, thus resulting in smaller equivalent dielectric thickness, as well as less interface states and dielectric charges. All these are attributed to the hydrolyzable property of GeOx in water. Moreover, the wet-N2 annealed capacitor has ten times lower gate-leakage current due to its better dielectric morphology as confirmed by atomic force microscopy.

Very Low Bit Error Rate in Flash Memory Using Tunnel Dielectrics Formed by Kr/O2/NO Plasma Oxynitridation

The gate leakage current which influences the charge hold time of flash memories is characterized as very localized in tunnel oxide area. And the leakage current value is relatively low as the quantity of the current. In conventional test-element-group (TEG) for evaluation of this leakage current, the gate leakage current is measured in relatively large area capacitors or transistors, as a result, the localized and low gate leakage current cannot be measured. In this paper, we propose the new concept TEG in which the localized gate leakage current corresponding to the bit error in the flash memory can be measured in short time. We statistically evaluated the stress induced leakage current (SILC) of all cells in very low gate leakage current region (about 10-16 A) in the very short time (a few seconds) and easily confirmed and categorized the localized cells with the large SILC after the stress. In addition, we show that plasma oxynitridation using Kr/O2/NO gases is effective in suppressing the anomalous SILC and carrier traps by statistically evaluation of 60,000 cells in proposed array TEG.

Enhanced device performance of AlGaN/GaN HEMTs using HfO2 high-k dielectric for surface passivation and gate oxide

AlGaN/GaN high electron mobility transistors (HEMTs) using HfO2 as a surface passivation layer and metal–oxide–semiconductor HEMTs (MOS-HEMTs) using HfO2 as gate oxide have been investigated and compared with the regular HEMTs. In MOS-HEMTs, the HfO2 gate dielectric is also used for passivation simultaneously. Our measurements have shown that both passivated HEMTs and MOS-HEMTs outperformed the regular HEMTs in dc, high-frequency and pulsed-mode operations, with MOS-HEMTs exhibiting the best characteristics, including the highest drain current, the lowest gate leakage current, the largest gate voltage swing, the highest cut-off frequencies and the best immunity to current collapse. In addition, the decrease in transconductance of MOS-HEMTs relative to HEMTs is as low as 8.7%, most probably a consequence of the high-k value of HfO2. Our results thus indicate the great potential of HfO2/AlGaN/GaN MOS-HEMTs for high-frequency and high-power applications.

Ultralow-power organic complementary circuits

The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices and large-surface sensor networks as well as for radio-frequency identification tags with extended operating range.

AlGaN/GaN HEMTs on free-standing GaN substrates: MBE growth and microwave characterization

We investigate the role of substrate temperature and gallium flux on the DC and microwave properties of AlGaN/GaN high electron mobility transistors grown by molecular-beam epitaxy on free standing, hydride vapor phase epitaxy grown GaN substrates. The free-standing substrates have threading dislocation densities below 10 7 cm −2. We find that AlGaN/GaN heterostructures with excellent properties may be grown within a wide range of substrate temperatures and fluxes. Electron Hall mobilities above 1700 cm 2/V s and sheet resistances below 370 Ω/□ are typical. We are able to obtain high saturated drain currents with low gate leakage. Off-state breakdown voltages as high as 200 V with low drain and gate leakage currents have been measured. Further, we have measured microwave output power densities above 5 W/mm at 4 GHz with a power-added efficiency of 46% and an associated gain of 13.4 dB. We attribute improved electrical properties in these devices to the reduced threading dislocation density compared to those grown on non-native substrates.

The Electrical Characterization of Molecular-Beam-Deposited LaAlO3 on GaAs and its Annealing Effects

AbstractThe electrical properties of Al/LaAlO3/GaAs metal-oxide-semiconductor capacitors were investigated. A thick arsenic (As2) capping layer was used to protect the GaAs from oxidation and contamination during the air exposure that occurred between the deposition of the GaAs and LaAlO3 layers in different molecular-beam epitaxy systems. Amorphous LaAlO3 was deposited on c(4×4)- and (2×4)-reconstructed (100) GaAs surfaces. Post dielectric deposition annealing was found to improve the capacitance-voltage (C-V) characteristics by eliminating frequency dispersion in the depletion and weak inversion regimes and diminished the bi-directional C-V hysteresis to 210 mV. Reasonably low gate leakage current was maintained after annealing.

Structure design criteria of dual-channel high mobility electron transistors

The design criteria of dual-channel high electron mobility transistor (DHEMT) are proposed in this study. δ-Doped In0.52Al0.48As/In0.53Ga0.47As/InP material systems are concentrated in this article. The DHEMT structures are explored numerically and compared with conventional single-channel high electron mobility transistor (SHEMT) structures. Some criteria of doping concentration and layer structure design are proposed. The simulation results reveal that DHEMT has a larger voltage swing, a lower gate leakage current, a better carrier confinement, a higher density of two-dimensional electron gas (2DEG) and an excellent transconductance than SHEMT.

Advanced HfTaON/SiO/sub 2/ gate stack with high mobility and low leakage current for low-standby-power application

A novel HfTaON/SiO/sub 2/ gate stack has been investigated for low-standby-power (LSTP) CMOS application. This gate stack exhibited good physical and electrical characteristics, including good thermal stability up to 1000 /spl deg/C, low gate-leakage current, excellent interface properties, and superior electron and hole mobility (100% and 96% of universal curves at 0.8 MV/cm). The excellent characteristics observed in HfTaON/SiO/sub 2/ suggest that it may be a very promising gate stack for advanced LSTP CMOS application.

Low Threshold-14 W/mm ZrO2/AlGaN/GaN Metal–Oxide–Semiconductor Heterostructure Field Effect Transistors

We report for the first time on the RF performance of a low-threshold AlGaN/GaN metal–oxide–semiconductor heterostructure field transistor (MOSHFET) with zirconium dioxide as the gate dielectric. Low gate leakage current of 5×10-7 A/mm2 and a threshold voltage which was only 1 V higher than that of an HFET were achieved. The RF power of these devices at 2 GHz was 14.32 W/mm at 50 V drain bias.

Characteristics of δ-doped InAlAs/InGaAs/InP high electron mobility transistors with a linearly graded InxGa1−xAs channel

Various static and microwave performances on InAlAs/InGaAs/InP HEMTs with a linearly-graded InxGa1−xAs channel (LGC-HEMT) have been comprehensively investigated and compared to those having a conventional lattice-matched In0.53Ga0.47As channel (LM-HEMT). Improved carrier transport characteristics and confinement capability by employing the linearly-graded channel have contributed to superior extrinsic transconductance (gm) of 346 mS mm−1, gate-voltage swing (GVS) of 0.5 V (182 mA), unity-gain cut-off frequency (ft) of 41 GHz and maximum oscillation frequency (fmax) of 63 GHz, with an improved frequency operation plateau at 300 K for a gate dimension of 0.65 × 200 µm2. Furthermore, improved kink effects leading to a lower gate leakage current of 0.7 µA mm−1, lower output conductance (gd) of 3.6 mS mm−1, higher voltage gain (AV) of 93.1, higher off-state breakdown voltage of 16.3 V and superior output power characteristics have also been discussed.

Photoresponse of gated p-silicon field emitter array and correlation with theoretical models

Improved fabrication and conditioning techniques for gated p-Si field emitter arrays (FEAs) (1×1mm2 in size with 50×50 emitters) greatly reduces the bulk damage and surface states. Consequently, only 0.9μA of the anode dark field-emission current was measured for 50V applied gate potential with a very low gate leakage current. At these low gate leakage currents, the transition between the tunneling-limited field-emission regime and the supply-limited saturation regime is clearly revealed in current-voltage plots. This transition is accompanied by a reduction in the anode current fluctuation. The standard deviation of the noise current drops from a few percent in the tunneling-limited regime to <1% in the supply limited regime at 50V. A photocurrent of 0.41mA was obtained for photoexcitation at 840nm wavelength. This corresponded to 40dB contrast ratio between the photocurrent and the dark current at room temperature. Additionally, our findings showed that surface states were fully depleted at low applied fields, the concentration of bulk defects was low and the area contributing to the dark current was confined to the emitter regions. In contrast, previously reported ungated Si field emitters had high concentrations of surface states and bulk defects. Furthermore, the contributing area to the dark current corresponded to the whole area of the device as opposed to only the emitter areas for a gated FEA. Photofield emission and dark current measurements from our gated p-Si FEA correlate well to theoretical models without requiring cooling to liquid-nitrogen temperatures.

Nitrogen profile engineering in the interfacial SiON in a HfAlO/SiON gate dielectric by NO Re-oxidation

The effects of the nitrogen profile in the SiON-interfacial layer (IL) on the mobility in FETs employing a HfAlO/SiON gate dielectric have been investigated. In order to suppress the interdiffusion between HfAlO and SiON, the nitrogen concentration in SiON should be higher than 15 at%, while the substrate interface should be oxygen-rich in order to suppress the mobility reduction. By using an NO reoxidation of NH/sub 3/ formed 0.4-nm-thick silicon nitride, the mobility reduction due to the SiON-IL was successfully suppressed, and electron and hole mobility of 92% and 88% of those for SiO/sub 2/ at V/sub g/=1.1 V were obtained for HfAlO/SiON with equivalent oxide thickness (EOT) of 1.1 nm. By using nitrogen profile engineered SiON-IL, good equvalent oxide thickness (EOT) uniformity, low EOT, low gate leakage current, low defect density, and symmetrical threshold voltage were all achieved, indicating that a poly-Si/HfAlO/SiON gate stack would be a candidate as an alternative gate structure for low standby power FETs of half-pitch (hp)65 and hp45 technology nodes.

Enhanced characteristics in gate-recessed and sidewall-recessed AlGaAs/InGaAs PHEMTs by citric-based selective wet etching

Improved device performance in Al0.2Ga0.8As/In0.15Ga0.85As gate-recessed enhancement-mode pseudomorphic high electron mobility transistors (E-PHEMTs) and sidewall-recessed depletion-mode PHEMTs (D-PHEMTs) using a newly developed citric buffer etchant are reported. The innovated etchant near room temperature (23°C) possesses a high GaAs/Al0.2Ga0.8As or In0.15Ga0.85As/Al0.2Ga0.8As etching selectivity (>250) applied to an etched stop surface. For E-PHEMTs, the transconductance (Gm) of 315 mS/mm and high linearity of 0.46 V-wide gate voltage swing (drop of 10% peak Gm), corresponding to 143 mA/mm-wide IDS, even at a gate length of 1 µm is obtained. For microwave operation, this 1 µm-gate E-PHEMT shows the fmax (maximum operation frequency) of 29.2 GHz and the fT (cut-off frequency) of 11.2 GHz, respectively. The measured minimum noise figure (NFmin), under VDS = 3 V and IDS = 7.5 mA, is 0.56 dB at 1 GHz with the associated gain of 10.86 dB. The NFmin is less than 1.5 dB in the frequency range from 1 to 4 GHz. In addition, an effective and simple method of selective gate sidewall recess is utilized to etch the low barrier in In0.15Ga0.85As channel at mesa sidewalls for D-PHEMTs. For D-PHEMTs with 1 × 100 µm2 exhibit a very low gate leakage current of 2.4 μA/mm even at VGD = −10 V and high gate breakdown voltage over 25 V. As compared to that of no sidewall recess, nearly two orders of reduction in magnitude of gate leakage current and 100% improvement in gate breakdown voltage are achieved.