Low Dropout Voltage Research Articles

Noise Aware Fully Integrated Low Power and Low Inrush Current Fast Transient Response LDO

The complexity of Systems-on-Chip (SoC) designs necessitates robust linear regulator architectures to ensure stable operations and efficient power management in modern devices. In response to this demand, low-dropout (LDO) voltage regulators have emerged as a focal point for their scalability and superior performance across diverse application domains. This paper proposes an LDO linear regulator characterized by high power supply rejection ratio (PSR) and rapid transient response. The design of this LDO emphasizes low power consumption and minimal inrush current while incorporating advanced techniques to enhance PSR and stability across varying frequencies. Despite its compact footprint and low-power profile, this LDO achieves remarkable PSR across a broad spectrum of frequencies. To achieve swift transient response, the proposed design integrates variable biasing and transient boost capacitance. The variable bias structure enhances the slew rate and PSR of the LDO, contributing to its overall performance optimization. Additionally, the strategic placement and utilization of transient-boost capacitance leverage its voltage characteristics to bolster transient response without introducing additional quiescent current, thereby further enhancing circuit stability.

A Transient-Enhanced Capacitorless LDO Design

Abstract This paper introduces a capacitor-less low drop-out voltage regulator (LDO) designed for fast transient response. Traditional capacitor-less LDOs often suffer from suboptimal transient responses, leading to unstable outputs during load transitions. To address this challenge, the circuit employs voltage rise and fall suppression circuits to mitigate voltage spikes. It utilizes slew rate enhancement techniques to improve the transient response characteristics of the LDO. Miller compensation is applied to achieve phase margin compensation with a smaller capacitor area. Simulation outcomes indicate that within the voltage range of 2.2 V to 3.3 V, the circuit provides a stable output voltage of 1.8 V while accommodating a peak load current of 100 mA. When the load current undergoes a step change between 1 mA and 100 mA, the transient enhancement circuit reduces the undershoot of the output voltage by 58 mV, a decrease of 39%, with a response time of 1.13 μs. The overshoot amplitude is reduced by 212 mV, a decrease of 70.6%, with a response time of 1.21 μs.

A 1.8 V, 10 mA low dropout voltage regulator for IoT application in 90 nm CMOS technology

A complementary metal-oxide-semiconductor CMOS low dropout voltage regulator (LDO) design flow using 90 nm CMOS technology is described and simulated in this paper. The circuit consists of an analogue LDO with using PMOS pass device, an error amplifier, a bandgap voltage, a biasing circuit, a feedback resistive network sized to have the desired closed loop gain. This LDO was designed to maintain stable voltage at 1.8 V and 10 mA of current output in low resistive load. The LDO regulator achieves 105 uA quiescent current, -47 PSRR@13 KHz noise frequency. The final design occupies approximately 0.05 mm<sup>2</sup>. The results were satisfying and make the designed circuit suitable for IoT application.

Hybrid low-dropout voltage regulator designed with TFET-MOSFET nanowire technologies

In this work, hybrid low-dropout voltage regulators (LDO) designed with a tunnel field-effect transistor (TFET)-MOSFET nanowire (NW) technologies are presented. The devices were modeled using Verilog-A with lookup tables based on experimental data of NW-TFETs and NW-MOSFETs fabricated in the same silicon vertical process flow. In all LDOs, the amplifier devices were biased with the same gm/I D = 9.5 V−1 for a maximum load current/capacitance of 1 mA/1 nF. In the hybrid regulators, the power transistors are designed with NW-MOSFETs to deliver the high load current, while the other devices are implemented with NW-TFET to provide high gain and low power consumption. Due to different onset voltages, two hybrid LDOs are proposed, one with symmetrical onset voltages implemented with a voltage shift (Hybrid-ΔV LDO) and one with a level-shift stage using the real characteristics of the devices (Hybrid-LS LDO). The hybrid circuits were compared to LDOs designed using only NW-TFETs and with only NW-MOSFETs. The Hybrid-ΔV LDO presents the best loop gain (62 dB) with a low quiescent current (7 nA), while the Hybrid-LS LDO shows a good gain-bandwidth product (700 Hz). In the transient analysis, the hybrid circuits showed a settling time close to the NW-MOSFET LDO but with higher undershoot/overshoot values in the case of a load transient. As demonstrated, the use of hybrid projects with TFET-MOSFET NW technologies enable LDOs with ultra-low power consumption and high loop gain, that are presented on TFET circuits and with a frequency response equivalent of MOSFET circuits.

A Low Power Low Inrush Current LDO with Different Techniques for PSR and Stability Improvement

One of the most popular power management regulators is the low drop-out voltage regulator (LDO). LDOs have different specifications such as the power supply rejection (PSR) over different frequencies, stability over different load ranges, inrush current spike flows through the input supply, and power consumption. In this work, we present a low power low inrush current LDO design with different techniques for PSR and stability improvement across different frequencies. The LDO presented in this work is a low-power and small area LDO but achieves a high PSR over a wide range of frequencies. The LDO is designed in 65 nm CMOS technology and achieves a PSR better than 80 dB up to 30 MHz for an output load current of 25 mA using an output load capacitor of 4 µF. The design can be used in capless/capped LDOs with wide load current ranges as high as 200 mA and load capacitor range from 1 nF to 12 µF with inrush current improvement by more than 2×. The presented LDO consumes a zero-load quiescent current of 10 µA and its area of 180 µm × 180 µm.

Low-Cost Structural Monitoring of Analog Circuits for Secure and Reliable Operation

The need for digital calibration due to large variations in fine-geometry processes as well as the need for performance locking mechanisms to prevent IC piracy have resulted in the prevalent use of digital assistance for analog circuits. In order to ensure the secure and reliable operation of the system, the performance of the analog circuits needs to be monitored in the field with robust, low-cost methods. In this paper, we propose a method reliant on monitoring simple invariants for detecting performance degradation of digitally-assisted analog circuits. We demonstrate the proposed method on two circuits: a low drop-out voltage regulator (LDO) and an active low-pass filter. Extensive Monte-Carlo simulations confirm that the proposed method detects deviations in performance due to tampering.

`Design-technology-co-hardening for voltage reference and linear voltage regulator based on bipolar technology

This article presents a radiation-hardened voltage reference and a radiation-hardened low-dropout (LDO) voltage regulator manufactured in bipolar technology for space environment applications. The output of voltage reference is adjustable in 2.5 V ∼ 30 V, with a supply voltage of 24 V. The LDO regulator operates from an input voltage range of 2.5–26 V and provides an output voltage of 1.5 V, with output voltage accuracy of ±0.5 %. The dropout voltage <700 mV at the full load current of 7A. It achieves line regulation and load regulation are <0.5 % over the entire operating temperature range. Through the circuit design of radiation hardening and the optimization of anti-radiation technology, both power management chips have single-event transient (SET) immunity at linear energy transfer (LET) of 37.4 MeV·cm2/mg. The output voltage deviation of rad-hard voltage reference is <0.6 % with total dose radiation tolerance of 100krad(Si) at 0.1 rad(Si)/s.

Accelerated ageing effects on the EMC performance of LDO regulators under multi-stresses: Experimental study and prediction approach

Low dropout voltage regulators (LDOs) play a crucial role in power management circuits. Unfortunately, long-term instability may threaten their functionality as well as their EMC performance, both concerning immunity and emission. The modeling of EMC deviations due to ageing degradation can assist to estimate the life expectancy of the LDOs and improve the reliability of the circuits. In this paper, a novel model is proposed to predict the conducted immunity deviations of LDOs based on convolutional neural networks and a long short-term memory (CNN LSTM) algorithm. It can explicitly learn the features of the conducted immunity in a wide frequency range and can accommodate multiple stresses which are applied to mimic the ageing process. The model is validated by carrying out an experiment where the DC (direct current) characteristics and conducted immunity performance are consistently monitored when the LDOs are subject to thermal-electrical-stresses in an ageing test. It can provide accurate immunity predictions and bypass the internal structure of the chips. It is shown that the proposed approach outperforms other models.

Low-Dropout Voltage Regulator Designed with Nanowire TFET with Different Source Composition Experimental Data

This paper presents the design of low-dropout volt-age regulators (LDO) using nanowire tunnel field-effect tran-sistors (TFETs) and nanowire MOSFET. The devices are mod-eled using lookup tables implemented with experimental measures of TFETs with different source compositions (Si, SiGe and Ge) and MOSFET. In order to compare the designs, the transistors of the differential amplifier in all LDOs is biased with gm/ID = 8 V-1 with a load of 1 μA and 10-pF. It is shown that all TFET based LDOs are stables without the need of a compensator capacitor (CC) even for higher load capacitance. For the MOSFET LDO, a CC of 5-pF capacitor was used. The study shows that the TFET based LDOs deliver higher effi-ciency due to the possibility to operate with low bias current. In the transient analysis it is shown that the TFET LDOs have lower overshoot but higher delay. The Ge-TFET LDO pre-sented settling times for load and line transient close to the MOSFET LDO with 15 μs and 30 μs. The SiGe-TFET LDO shows the best loop gain (60 dB), while the Si-TFET LDO deliv-ers lowest quiescent current (300 pA) and the Ge-TFET have the best GBW (70 KHz) and PSR (-52 dB). It is concluded that the TFET based LDOs can deliver specifications similar or bet-ter than the MOSFET LDO even without the need of CC and with less power consumption.

A 64-MHz 2.15-µW/MHz On-Chip Relaxation Oscillator with 130-ppm/°C Temperature Coefficient

This paper presents a 2.15 µW/MHz at the frequency of 64 MHz relaxation oscillator with a dynamic range of frequency from 47.5 MHz to 80 MHz. To reduce the power consumption and improve energy efficiency, this work employs only one comparator and one capacitor to generate the output clock in comparison with conventional relaxation oscillator structures. A total of 50% ± 5% of the duty cycle is obtained for the output clock by implementing an auxiliary comparator. The proposed relaxation oscillator uses the output voltages of an external low-dropout (LDO) voltage and bandgap reference (BGR) for the required supply and reference voltages, respectively. Two current sources are implemented to provide the required currents for trimming the output frequency and driving the comparators. Measurement results indicate that the relaxation oscillator achieves a temperature coefficient (TC) of 130 ppm/°C over a wide temperature range from −25 °C to 135 °C at the frequency of 64 MHz. The relaxation oscillator consumes 115 µA of current at the frequency of 64 MHz under a low-dropout (LDO) voltage of 1.2 V. The proposed relaxation oscillator is analyzed and fabricated in standard 90 nm complementary metal-oxide semiconductor (CMOS) process, and the die area is 130 µm × 90 µm.

Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis

This work presents the comparison between Nanowire Tunnel Field-Effect Transistor (NW-TFET) and Line-TFET applied on the design of Low-Dropout Voltage Regulator (LDO). Both devices have a SiGe source composition in order to enhance the current drive. The transistors were modeled using lookup tables (LUTs) approach based on experimental data using Verilog-A language. The LDOs were designed for two conditions, considering different gm/ID, load currents and load capacitances. In order to compare the TFET LDOs with an established technology, a MOSFET LDO was designed with TSMC 0.18 µm process design kit. Both TFET LDOs reach stability without the presence of a compensation capacitor. For gm/ID = 10.5 V−1 the current consumption of NW-TFET LDO (1.5nA) is near two orders of magnitude lower than Line-TFET LDO (68nA) and three orders of magnitude lower than MOSFET LDO (9 µA). The Line-TFET LDO exhibits better results in almost all parameters despite of the gain-bandwidth product (GBW) that is in the same order of magnitude of the MOSFET LDO, 171 kHz compared to 250 kHz for gm/ID = 10.5 V−1. The comparison between TFET LDOs for gm/ID = 7 V−1 was also performed regarding the transient and process variability analysis. The transient response revealed that the Line-TFET LDO has a pronounced lower settling time, 71 µs compared to 5 ms for a load step, but with a damped oscillatory response, the NW-TFET LDO presented lower undershoot for the load step. The process variability analysis was performed for devices within the wafer and was observed that the Line-TFET LDO suffers a higher impact with a 20 dB variation on the loop gain in comparison to 10 dB in the NW-TFET LDO.

A Low Cost Self-Adaptive Screening Method Based on Automatic Test Equipment for Low Dropout Voltage Regulators in Mass Production

A Low Cost Self-Adaptive Screening Method Based on Automatic Test Equipment for Low Dropout Voltage Regulators in Mass Production

Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low Voltage Mobile Applications: A Review

Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low Voltage Mobile Applications: A Review

Design Automation of Low Dropout Voltage Regulators: A General Approach

Analog design is an inherently intricate process comprising many trade-offs; as a result, it is an iterative time-consuming operation. A low dropout voltage regulator (LDO) is an example of such analog blocks that involve a myriad of trade-offs. In this paper, we present an automated design procedure for LDOs using precomputed look-up tables (LUTs) and the gm/ID methodology. Using a symbolic solver and the precomputed LUTs, a design database for an LDO that contains one million design points is generated in a few seconds. The database provides visualization of the design space and exploration of the trade-offs across different corners and load currents. A design example is provided to demonstrate the procedure using 40 nm technology and the results are verified using Cadence Spectre simulator. The approach is holistic in the sense that it uses an accurate symbolic solver to capture the small signal model complexities, incorporates LUTs for accurate calculation of the large signal solution and the small signal parameters, is fast because the simulator in the loop scenario is omitted, and almost all the specifications of LDOs are incorporated.

A Low-Voltage and Power-Efficient Capless LDO Based on the Biaxially Driven Power Transistor Technique for Respiration Monitoring System.

In this study, a 0.8-V- Vin 200-mA- Io capless low-dropout voltage regulator (LDO) is developed for a wireless respiration monitoring system. The biaxially driven power transistor (BDP) technique is proposed in the LDO, with a current driven stimulation on the bulk and a voltage on the gate terminal. With the BDP technique, an adaptively biased current-driven loop (ABCL) is designed which can reduce the high threshold voltage of power transistor, thus presenting lower input voltage and reduced power consumption. Moreover, this loop can provide an improved dynamic response due to its increased discharging current. Based on an error amplifier with enhanced DC gain and gain bandwidth, the capless LDO achieves superior power supply rejection (PSR) and stability without a complex frequency compensation mechanism. The proposed LDO is fabricated in the SMIC 180 nm process with a chip area of 0.046 mm 2. Measurement results indicate that this LDO can obtain a 200-mA load current range and greater than -66 dB PSR up to 1 kHz at a supply voltage as low as 0.8 V.

A low power high area-efficiency NMOS LDO with fast adaptive bias

A low power consumption and fast transient response NMOS low dropout voltage regulator (LDO) with fast adaptive bias is proposed in this work. As a buffer between error amplifier and pass device in LDO, the symmetric flipped voltage follower could ensure stability and speed up the load transient response. In order to obtain better transient response performance and lower power consumption at quiescent state, an adaptive bias is used to generate adaptive current in different proportions, from load current to error amplifier and symmetric flipped voltage follower. The proposed LDO is designed in a 180 nm CMOS process with only 0.005 mm2 active area. Under the condition of typical process corner, the DC loop gain is at least 42.81 dB, and the phase margin ranges between 51.6° and 113.6°. Despite only 2.91μA quiescent current, the LDO with sub-microsecond settling time as low as 1ns at the edge of the load current change has little overshoot/undershoot.

Compact Low-dropout Linear Regulator Design in 0.13 µm CMOS Technology for IoT Based Remote Infectious Disease Monitoring System

With the widespread adoption of the internet of things (IoT), power management of the different electronic (i.e. IoT) devices has become a major challenge. The low-dropout linear regulator (LDO) circuit is widely used for power management applications of electronic devices. This article reports the design and simulation of a low-dropout linear regulator (LDO) circuit, powered by a 1.2 V DC power supply voltage. In order to optimise the power dissipation, low layout silicon area and lower dropout voltage, a current mirror based transistor optimised LDO circuit has been implemented. The simulation results show that the proposed LDO regulator circuit exhibits a 582 mV low-dropout voltage, 1.568 mW power dissipation, and a very compact layout silicon area of 163.84 µm 2(12.795 × 12.805 µm). The proposed LDO linear regulator archi- tecture is designed and validated in 0.13 µm TSMC CMOS process technology using Mentor Graphic EDA tools.

Design of high reliability LDO regulator with NLRSCR based ESD protection circuit using dynamic feedback loop for low-voltage applications

Capacitor-less low dropout voltage regulator applied to the mobile devices consistently exposes the peak voltage, which can increase the power consumption. This study proposes a dynamic feedback loop of the LDO regulator that provides a function to stably control the peak voltage irrespective of the change of the load current. The performance of the chip layout was evaluated under conditions of an output voltage of 3 V, a battery input voltage of 3.3 to 4.5 V, and a load current of 350 mA. As a result, the peak voltage keeps an undershoot voltage of 30 mV and an overshoot of 33 mV along the load current. In addition, the demand for miniaturization and integration of ICs and the application of low voltage applications are increasing. Thereby, the circuit damage due to ESD (Electro Static Discharge) may happen frequently. This is a significant factor influencing the overall reliability related to productivity and stability. In this study, we confirmed that the proposed LDO regulator with the ESD protection circuit of the NLRSCR structure secures high reliability at low voltage.

A Lightweight Power Side-Channel Attack Protection Technique With Minimized Overheads Using On-Demand Current Equalizer

A lightweight on-demand current equalizer is proposed in this brief to enhance the resistance of the encryption engine to power side-channel attack (PSCA) with a minimized performance-power-area (PPA) overhead. The proposed on-demand current equalizer is operated based on the real-time activity of the encryption engine to minimize the corresponding current signature leakage, while enhancing the supply quality by reducing the voltage droop. Therefore, an encryption engine employing the proposed PSCA protection technique has a low power overhead without suffering from any performance degradation. In addition, an embedded randomization method is proposed to further strengthen the resistance of the encryption engine to PSCA while maintaining the power supply quality. A prototype chip that integrates the proposed design, a 128-bit advanced encryption standard (AES) engine, and a digital low-dropout voltage regulator (DLDO) was fabricated in 180-nm CMOS technology. Measurement results show that the proposed design achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$234{\times }$ </tex-math></inline-formula> minimum traces to disclose (MTD) improvements in correlation power analysis (CPA), with no performance overhead, 21.17% power overhead, and 32.88% area overhead, respectively.

Digital Fault-based Built-in Self-test and Evaluation of Low Dropout Voltage Regulators

With increasing pressure to obtain near-zero defect rates, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, power converters, and data converters. This article presents an extremely low-cost built-in self-test technique for LDOs, specifically designed for fault detection. The methodology relies on exciting the LDO loop at the voltage reference input via a pseudo-random signal with white noise characteristics and observing the response from the output of LDO via all-digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with an LDO as a device under test is designed in 65nm technology. Fault simulations performed at the transistor level show that all resistive open/short defects in circuit components can be detected even if they do not cause a catastrophic failure in the LDO response. The proposed technique is validated with hardware using off-the-shelf components.