Abstract
Abstract This paper introduces a capacitor-less low drop-out voltage regulator (LDO) designed for fast transient response. Traditional capacitor-less LDOs often suffer from suboptimal transient responses, leading to unstable outputs during load transitions. To address this challenge, the circuit employs voltage rise and fall suppression circuits to mitigate voltage spikes. It utilizes slew rate enhancement techniques to improve the transient response characteristics of the LDO. Miller compensation is applied to achieve phase margin compensation with a smaller capacitor area. Simulation outcomes indicate that within the voltage range of 2.2 V to 3.3 V, the circuit provides a stable output voltage of 1.8 V while accommodating a peak load current of 100 mA. When the load current undergoes a step change between 1 mA and 100 mA, the transient enhancement circuit reduces the undershoot of the output voltage by 58 mV, a decrease of 39%, with a response time of 1.13 μs. The overshoot amplitude is reduced by 212 mV, a decrease of 70.6%, with a response time of 1.21 μs.
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