Compact Low-dropout Linear Regulator Design in 0.13 µm CMOS Technology for IoT Based Remote Infectious Disease Monitoring System

Abstract

With the widespread adoption of the internet of things (IoT), power management of the different electronic (i.e. IoT) devices has become a major challenge. The low-dropout linear regulator (LDO) circuit is widely used for power management applications of electronic devices. This article reports the design and simulation of a low-dropout linear regulator (LDO) circuit, powered by a 1.2 V DC power supply voltage. In order to optimise the power dissipation, low layout silicon area and lower dropout voltage, a current mirror based transistor optimised LDO circuit has been implemented. The simulation results show that the proposed LDO regulator circuit exhibits a 582 mV low-dropout voltage, 1.568 mW power dissipation, and a very compact layout silicon area of 163.84 µm 2(12.795 × 12.805 µm). The proposed LDO linear regulator archi- tecture is designed and validated in 0.13 µm TSMC CMOS process technology using Mentor Graphic EDA tools.