Design of high reliability LDO regulator with NLRSCR based ESD protection circuit using dynamic feedback loop for low-voltage applications

Abstract

Capacitor-less low dropout voltage regulator applied to the mobile devices consistently exposes the peak voltage, which can increase the power consumption. This study proposes a dynamic feedback loop of the LDO regulator that provides a function to stably control the peak voltage irrespective of the change of the load current. The performance of the chip layout was evaluated under conditions of an output voltage of 3 V, a battery input voltage of 3.3 to 4.5 V, and a load current of 350 mA. As a result, the peak voltage keeps an undershoot voltage of 30 mV and an overshoot of 33 mV along the load current. In addition, the demand for miniaturization and integration of ICs and the application of low voltage applications are increasing. Thereby, the circuit damage due to ESD (Electro Static Discharge) may happen frequently. This is a significant factor influencing the overall reliability related to productivity and stability. In this study, we confirmed that the proposed LDO regulator with the ESD protection circuit of the NLRSCR structure secures high reliability at low voltage.