Low-dropout Regulator Research Articles

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review

Low-dropout regulators (LDOs) are widely adopted in power management integrated circuits (PMICs) and serve as a bridge between the switching regulators and individual on-chip modules to provide a smooth, regulated output voltage. Compared to digital LDOs (DLDOs), analog LDOs (ALDOs) lead in the advantage of low output ripple and large power supply rejection (PSR). However, the preference of achieving high performance in terms of load transient, high PSR, good load and line regulation, while maintaining a low quiescent current and low dropout voltage for high efficiency, remains the key challenge in ALDO design. For operation with a low quiescent current, the bandwidth is reduced due to low transconductance, resulting in the limited gate driving capabilities in terms of charging and discharging the large gate capacitance of the pass or output transistor. In addition, the preference for system-on-chip design in the absence of large off-chip capacitors arises stability issues. In this paper, recent reported state-of-the-art architectures for ALDOs are revisited and reviewed. The performance of these ALDOs is compared and their applications are investigated.

A capacitor-free fast-response low-dropout voltage regulator

An off-chip capacitor-free low-dropout (LDO) regulator using an improved frequency compensation scheme is proposed. The proposed LDO regulator employs a class-AB error amplifier and a load-current tracker. Outstanding line regulation, load regulation and transient response are achieved. SPICE simulation based on SMIC 0.35 µm CMOS technology shows that the proposed LDO regulator has a low frequency gain over 100 dB and a unity-gain bandwidth in the MHz range. In terms of transient response, the 1% settling time is shorter than 0.2 µs.

Online Broadband Battery Impedance Spectroscopy Using Current-Mode Boost Converter

In this paper an online method of broadband battery impedance spectroscopy is proposed in which the excitation signal is injected through the inner feedback loop of a DC/DC boost converter with average current-mode control (ACMC). By deriving the average state-space model of the conventional boost converter, it is shown that an open-loop converter exhibits a resonant frequency response in regards to the injected signal, whereas the compensated current loop in ACMC produces a controllable, flat-gain closed-loop transfer function that allows broadband current excitation signals to be injected into the battery without the distortion that is seen in the open-loop configuration. In the presented method, the converter is set to discharge the battery at a constant C-rate during impedance measurement while a broadband signal is superimposed onto the loop reference current. A low-dropout regulator is then used to filter out disturbances caused in the converter output. The proposed approach is experimentally implemented and a discrete-interval binary sequence signal is utilized to measure the impedance of two 18650 lithium-ion batteries in several arbitrary frequencies at once in the 0.1Hz-1kHz range. The measured spectra are validated by a commercial impedance analyzer.

Multiphase Digital Low-Dropout Regulators

In this work, multiphase digital low-dropout (MP-DLDO) regulators are designed with resonant rotary clocks (ReRoCs) in order to improve on the tradeoff of conventional DLDOs between current efficiency and transient response speed. The proposed DLDOs are multiphased, coined MP-DLDOs, designed with a clock-gated control technique to provide high current efficiencies along with transient response improvements at GHz frequency levels. The multiple phases within the MP-DLDO are served with ReRoCs that provide: 1) a robust high-speed low-power resonant clock distribution solution for the synchronous elements in the multiphase DLDO architecture and 2) improve the transient response characteristics (dynamic voltage scaling (DVS) speed and voltage ripple) while saving power in the controller circuitry. The proposed MP-DLDOs are distributed across the chip to achieve low voltage ripple. SPICE simulations are performed on post-layout, parasitic-extracted models to evaluate the MP-DLDO architecture on open-source digital cores, with performance metrics that include the voltage ripple reduction, transient response speed improvement, and power savings in the control logic. The proposed MP-DLDO architecture, evaluated on an RISC-V design, demonstrates a DVS speed of 6.5 V/μs and an output voltage ripple of 21.1 mV (38% reduction when compared to a conventional DLDO) with a sampling frequency of 2 GHz.

A Hybrid Low-Dropout Regulator With Load Regulation Correction

A hybrid low-dropout regulator (LDO) based on proposed load-regulation correction (LRC) is presented in this paper. The proposed hybrid LDO operates at an ultra-low supply of 0.6 V. It provides fast load transient response by proposed three-level switching and achieve high output accuracy by proposed LRC. The hybrid LDO is implemented in a 65-nm CMOS technology. The normalized error of dc output voltage and figure-of-merit are 0.0067 V/V and 0.4755 ns, respectively.

A 1.55-mW 2-GHz ERBW 7-b 800-MS/s Pipelined SAR ADC in 28-nm CMOS Using a 7T Dynamic Residue Amplifier

This letter presents a 3-stage pipelined successive-approximation-resister (SAR) analog-to-digital converter (ADC) using a seven transistor-dynamic residue amplifier (7T-DA) for kickback noise cancelation. Thanks to the pipeline structure, the input capacitance is only 16 fF, achieving an effective resolution bandwidth (ERBW) of 2 GHz. The gain sensitivity to the temperature of the dynamic amplifier is reduced by an on-chip low-dropout voltage regulator (LDO) and a pulse generator. Fabricated in the 28-nm CMOS process, the prototype ADC running at 800 MS/s achieves a peak SNDR of 42.7 dB and SFDR of 52.0 dB at Nyquist input. It also achieves SNDR of 38.9 dB and SFDR of 49.9 dB at a 2-GHz input. The total power consumption of ADC is 1.55 mW, which corresponds to the Waldon figure of merit of 17.4 fJ/conv step and Schreier FoM of 156.8 dB, respectively.

A Hybrid Low-Dropout (LDO) Regulator Using a Load Replication Circuit for DRAM Cores

This paper presents a cost-effective hybrid low drop-out regulator (LDO) circuitry for state-of-the-art DDR DRAM cores that not only supports various refresh operations, but also meets the JEDEC specification of the refresh period by improving the load-transient response. In order to guarantee a stable output voltage by achieving the precise off-control operation, a load replication circuit with dummy DRAM cells is exploited. The proposed cost-effective LDO has been implemented and fabricated in a standard 180nm CMOS technology and occupies 0.165mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . By adopting the hybrid LDO, voltage droop improvements of 62mV and 110mV, and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t_RFC</i> gain of 100ns and 120ns are measured with refresh rates of 4K and 8K, respectively. The measured current consumption overhead by 8 hybrid LDOs is 36μA during the 8K refresh operation. The peak current efficiency is 99.6% at a supply voltage of 1.2V.

A Low-Power Wide-Load-Range Output-Capacitorless Low-Dropout Voltage Regulator With Indirect-Direct Nested Miller Compensation

This paper presents the design of an output-capacitorless low-dropout voltage regulator (OCL-LDO) capable of driving a wide range of load capacitance and supplying a wide range of load current while maintaining excellent load and line regulations, thanks to the combined indirect-direct nested Miller compensation which ensures stability and maintains a high loop gain over the whole range of load condition. Fabricated in a 0.18-&#x03BC;m CMOS process and consuming 14 &#x03BC;A of quiescent current, the OCL-LDO, while supplying the load current between 0 mA to 100 mA, is capable of driving the load capacitance in the range of 0-1 nF; with a minimum load current of 1 mA, however, the OCL-LDO can drive up to 10 nF of load capacitance. Over such wide load-current and load-capacitance ranges, the OCL-LDO achieves DC load and line regulations of 0.025 mV/mA and 0.5 mV/V, respectively.

A 10 nA Ultra-Low Quiescent Current and 60 ns Fast Transient Response Low-Dropout Regulator for Internet-of-Things

Ultra-low quiescent current (<inline-formula> <tex-math notation="LaTeX">$I_{Q}$ </tex-math></inline-formula>) low-dropout regulator is the only solution for compact size Internet of Things (IoT) electronic devices. This paper presents an ultra-low <inline-formula> <tex-math notation="LaTeX">$I_{Q}$ </tex-math></inline-formula> low dropout regulator, including low <inline-formula> <tex-math notation="LaTeX">$I_{Q}$ </tex-math></inline-formula> error amplifier (EA) compensated by the adaptive current control (ACC), low leakage feedback network, low <inline-formula> <tex-math notation="LaTeX">$I_{Q}$ </tex-math></inline-formula> current comparator, analog transient enhancement (ATE), and digital transient enhancement (DTE). The chip was fabricated in a standard <inline-formula> <tex-math notation="LaTeX">$0.5~\mu \text{m}$ </tex-math></inline-formula> CMOS process. Measurement results show the current peak efficiency of the LDO is as high as 99.99&#x0025;. Besides, owing to ATE and DTE circuits, when the load current changes from 1mA to 50mA with a 10 ns edge time, the measured undershoot and overshoot voltages are 75 mV and 50 mV, respectively, with the recovery time (<inline-formula> <tex-math notation="LaTeX">$T_{R}$ </tex-math></inline-formula>) of 60 ns and 80 ns, respectively, where the best 0.003 ps FoM is achieved.

A Low-Band Multi-Gain LNA Design for Diversity Receive Module with 1.2 dB NF.

This paper presents and discusses a Low-Band (LB) Low Noise Amplifier (LNA) design for a diversity receive module where the application is for multi-mode cellular handsets. The LB LNA covers the frequency range between 617 MHz to 960 MHz in 5 different frequency bands and a 5 Pole Single Throw (5PST) switch selects the different frequency bands where two of them are for the main and three for the auxiliary bands. The presented structure covers the gain modes from −12 to 18 dB with 6 dB gain steps where each gain mode has a different current consumption. In order to achieve the Noise Figure (NF) specifications in high gain modes, we have adopted a cascode Common-Source (CS) with inductive source degeneration structure for this design. To achieve the S11 parameters and current consumption specifications, the core and cascode transistors for high gain modes (18 dB, 12 dB, and 6 dB) and low gain modes (0 dB, −6 dB, and −12 dB) have been separated. Nevertheless, to keep the area low and keep the phase discontinuity within ±10, we have shared the degeneration and load inductors between two cores. To compensate the performance for Process, Voltage, and Temperature (PVT) variations, the structure applies a Low Drop-Out (LDO) regulator and a corner case voltage compensator. The design has been proceeded in a 65-nm RSB process design kit and the supply voltage is 1 V. For 18 dB and −12 dB gain modes as two examples, the NF, current consumption, and Input Third Order Intercept Point (IIP3) values are 1.2 dB and 16 dB, 10.8 mA and 1.2 mA, and −6 dBm and 8 dBm, respectively.

A Bootstrap Structure Directly Charged by BUS Voltage with Threshold-Based Digital Control for High-Speed Buck Converter

This article proposes a high-frequency, area-efficient high-side bootstrap circuit with threshold-based digital control (TBDC) that is directly charged by BUS voltage (DCBV). In the circuit, the voltage of the bootstrap is directly obtained from the BUS voltage instead of the on-chip low dropout regulator (LDO), which is more suitable for a high operating frequency. An area-efficient threshold-based digital control structure is used to detect the bootstrap voltage, thereby effectively preventing bootstrap under-voltage or over-voltage that may result in insufficient driving capability, increased loss, or breakdown of the power device. The design and implementation of the circuit are based on CSMC 0.25 µm 60 V BCD technology, with an overall chip area of 1.4 × 1.3 mm2, of which the bootstrap area is 0.149 mm2 and the figure-of-merit (FOM) is 0.074. The experimental results suggest that the bootstrap circuit can normally operate at 5 MHz with a maximum buck converter efficiency of 83.6%. This work plays a vital role in promoting the development of a wide range of new products and new technologies, such as integrated power supplies, new energy vehicles, and data storage centers.

A Hybrid-Mode LDO Regulator with Fast Transient Response Performance for IoT applications

A hybrid-mode low-drop out (LDO) voltage regulator with fast transient response performance for IoT applications is proposed in this paper. The proposed LDO regulator consist of two sections. First section is an analog regulator which includes a folded cascode operational amplifier to achieve good PSRR. Second section is current DAC and detectors whitch includes a cource current DAC, sink current DAC, undershoot detectors, and overshoot detectors. The current DAC and detectors are designed to obtain a low drop out and fast transient response. The proposed hybrid-mode LDO voltage regulator has been designed, simulated and layouted in Cadence using TSMC 90 nm CMOS technology. The input range of the LDO regulator is 1.2–2.0 V, and it can produces an output voltage of 1.2V. The LDO regulator achieves 58uA quiescent current, -69 PSRR @ 1 KHz noise frequency and an output voltage drop of around 60mV for a load current step of 100 mA. The final design occupies approximately 0.09 mm2.

A fast-transient low-dropout regulator (LDO) with Super Class-AB OTA

This paper presents a low power fast transient low-dropout regulator (LDO) employing a Super Class-AB operational transconductance amplifier (OTA). The proposed structure not only achieve large charging/discharging current at the gate of power transistor but also a gain factor, which not only shows excellent transient performance but also ensures enough line/load regulation. Without adding addition circuit structure, the proposed LDO demonstrates a comprehensive improvement, including enhanced line/load regulation and transient performance, when compared with conventional counterpart, implemented in 0.18 μm CMOS technology, the proposed LDO shows a transient voltage variation of 53 mV at Vout for a load step of 10 μA-200 mA and possesses a line/load regulation of 1.25 mV/V and 100 μV/mA respectively.

Highly Efficient Fully Integrated Multivoltage-Domain Power Management With Enhanced PSR and Low Cross-Regulation

Multivoltage domains are urgently needed in modern system on chips (SoCs), while existing solutions such as switched dc−dc converter, switched capacitor converter, and low-dropout regulator (LDO) do not generate multivoltage domains conveniently and inexpensively. This article presents a highly efficient fully integrated power management strategy to provide the multiple voltage domains. The proposed architecture stacks a main LDO and several auxiliary push−pull regulators (APPRs) to generate multiple voltages for various loads in one SoC chip. The APPR regulates the load current by either absorbing or providing the additional current, which stabilizes the output voltages, increases the power supply rejection (PSR) and decreases the cross-regulation. A prototype with two output terminals is implemented with a standard 0.18- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m CMOS technology. The whole system achieves high power efficiency of 96.5% and high PSR of −62 and −142 dB for upper and lower outputs, respectively. The chip area is 980 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m × 500 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m and the total quiescent current is 239 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> A. In addition, all off-chip components are eliminated, which is favorable for monolithic realization. The reduced system cost and the reduced electromagnetic interference also simplify the power management significantly, which helps to enable low-power and compact SoCs.

A Non-Contact Compact Portable ECG Monitoring System

Cardiovascular diseases (CVDs) have been listed among the most deadly diseases worldwide. Many CVDs are likely to manifest their symptoms some time prior to the onset of any adverse or catastrophic events, and early detection of cardiac abnormalities is incredibly important. However, traditional electrocardiography (ECG) monitoring systems face challenges with respect to their scalability and affordability as they require direct body contact and cumbersome equipment. As a step forward from the large-scale direct-contact ECG monitoring devices, which are inconvenient for the user in terms of wearability and portability, in this research, we present a small-sized, non-contact, real-time recording system for mobile long-term monitoring of ECG signals. The device mainly comprises three non-contact electrodes to sense the bio-potential signal, an AD8233 AFE IC to extract the ECG signal, and a CC2650 MCU to read, filter, and transmit them. The device is powered by a 2000 mAh lithium-ion battery with isolation between digital and analog powers on the board using two low-dropout regulators (LDOs). The board’s dimension is 8.56 cm × 5.4 cm, the size of a credit card, making it optimal to be worn in a shirt chest pocket. In spite of its small form factor, the device still manages to achieve a continuous measurement battery life of over 16 h, total harmonic distortion below −30 dB across the interested frequency range, an input-referred noise as low as 1.46 µV for contacted cases and 5.15 µV for non-contact cases through cotton, and clear ECG recording for both contact and non-contact sensing, all at a cost around USD 50.

A CMOS standard-cell based fully-synthesizable low-dropout regulator for ultra-low power applications

This article presents a fully-synthesizable digital voltage regulator for applications with extremely low power consumption. The proposed design uses a synthesizable controller (DLDOC) to detect load fluctuations and control a tri-loop structural design. This tri-loop structure minimizes the ripples on output voltage (VOUT) and provides a fast-transient response (TR). This structure decreases the length of bi-directional shift register (Bi-SR) which reduces the overall power consumption. A quivering control is introduced to minimize the VOUT oscillations in steady-state. To demonstrate this design using CMOS standard-cells, a fully-synthesizable comparator (FS-comp) is utilized. A tri-state buffer array (TBA) is employed instead of conventional PMOS switch array to make this design fully-synthesizable. A pattern detection mechanism is used to switch between different loops. The proposed prototype occupies 6394 µm2 area in 45 nm CMOS technology. This design is implemented using conventional synthesis and place-and-route (P & R). For a supply voltage (VDD) of 0.5–1 V, a regulated VOUT is attained with a dropout voltage of 50 mV. At 10 MHz clock frequency, the proposed LDO achieves a quiescent current (IQ) and fast-TR of 2.2 µA and 300 ns, respectively. A maximum current efficiency (C.E.) of 99.98% is attained with output ripples < 1 mV.

A Low Power Voltage Spike Detection Circuit for Cap-less LDO

ABSTRACT A low-power voltage spike detection (VSD) circuit for a cap-less low-dropout regulator (LDO) is presented in this paper. The LDO is based on the cascoded flipped voltage follower (CAFVF) topology, and the transients in the output voltage are controlled by the spike detection circuits and these circuits get activated only during the transient period. The overshoot voltage spike detection (OVSD) circuit senses the output voltage via intermediate voltage and reduces the current through the power MOSFET by charging the gate capacitance and restores the output voltage whenever the output voltage rises. The undershoot voltage spike detection (UVSD) circuit directly detects the output voltage and increases the current through the power MOSFET by discharging the gate capacitance and restores back the output voltage whenever the output voltage drops. The VSD circuit consumes only a bias current of in the steady state. This LDO is implemented in CMOS technology and achieved a good load transient response with settling time with the maximum voltage spike of over the load current range of to .

0.5–1-V, 90–400-mA, Modular, Distributed, 3 × 3 Digital LDOs Based on Event-Driven Control and Domino Sampling and Regulation

This article presents on-chip power delivery hardware comprised of nine event-driven (ED) digital low-dropout voltage regulators (LDOs) for a large digital load. The goal is to address the performance degradations in an LDO's accuracy and dynamic load regulation in the presence of parasitics in the power grid of a load. In particular, we investigate the effects of power grid resistance ( R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ), which becomes worse with the size of a digital load and technology scaling. Two critical problems that we address are: 1) the IR drop and 2) the dynamic voltage droop problems. Employing multiple LDOs across the power grid improves the IR drop for mainly better voltage sensing. To tackle the voltage droop problem, we distribute LDOs with ED control such that the LDO closest to a localized droop can instantly correct it. To further improve the feedback control latency, we also enhance each LDO with a novel domino sampling and regulation technique. We prototype the on-chip power delivery system consisting of 3 ×3 digital LDOs in a 65-nm CMOS. We also devise the framework to analyze the stability of the multi-LDO system across R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> values. Measurements show that at 0.5-V (1 V) input, the single LDO exhibits 49.8-mV (94.1 mV) voltage droop for a load current change of 4.04 mA/0.1 ns (13.8 mA/0.2 ns) with a 0.1-nF integrated output capacitor. Also, the nine-LDO system achieves a current density of 248.8 mA/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (1.118.6 A/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) at 0.5-V (1 V) input voltage.

High-PSRR Low-dropout Regulator with Fast Transient Response Time and Low Output Peak Voltage

This study proposes the feed-forward ripple cancellation (FFRC) technique to low drop-out (LDO) regulator. By adding load tracking impedance to the gate of pass transistor, it is possible to secure stability with a 100-nF capacitor having low ESR and be obtained less than 35 ㎱ response time. In all frequency bands, a power supply rejection ratio (PSRR) less than -70 ㏈ is obtained when the load current is 10 ㎃. The circuit is implemented in 65-㎚ CMOS process.