Abstract
Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.
Highlights
The level of integration of modern electronic circuitries has increased in the last few years, because of the advancement of complementary metal–oxide–semiconductor (CMOS)technology, resulting in compact as well as low-cost electronic appliances [1,2]
This review presents an overview strategies reported in the literature to build high-performance linear regulators, especially of the design strategies reported in the literature to build high-performance linear regulalow-dropout (LDO), that are proven as convenient for versatile applications
This article reviewed the linear regulators in CMOS technology developed by previous researchers
Summary
The level of integration of modern electronic circuitries has increased in the last few years, because of the advancement of complementary metal–oxide–semiconductor (CMOS). A load lineartransient regulator can provide high-speed variations in the output signalefficiency and can a faster response. It causes poor performance in current generate a faster load transient response. Efficiency canasbeexternal measured by the regulation dropout voltage [18] Several condiconditionsthat such compensation of theFET’s regulators, output capacitance, and partions as external of the regulators, capacitance, and parasitic capacasiticsuch capacitance ofcompensation the output capacitor affect theoutput response of the regulators to a load transient [19].
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